Semiconductor Wiring via 3D Hole Conductor
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Solution Overview
Problem
Existing methods for manufacturing large-area semiconductor devices using dividing exposure techniques face challenges in achieving miniaturization of wiring patterns while maintaining yield and reliability, particularly when alignment shifts occur, leading to increased resistance and potential discontinuity of patterns across adjacent regions.
Innovation Solution
A method involving the arrangement of insulation films on a substrate, forming holes and trenches using photoresist patterns, and embedding conductors, where the holes are deeper than the trenches, and the trenches communicate with each other, allowing for a wiring pattern that spans adjacent regions with overlapping edges to ensure continuity and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of auxiliary pattern is increased to maintain continuity across regions, then alignment shift tolerance is improved, but wiring pattern miniaturization becomes difficult
Solution Approach 1:
The invention transitions from a two-dimensional surface connection to a three-dimensional structure by forming a hole that penetrates through the insulation film. The auxiliary pattern is connected not only laterally but also vertically through the hole, creating a 3D conductive path that maintains continuity without requiring increased lateral dimensions.
Solution Approach 2:
The auxiliary pattern is nested within the hole structure, where the conductor is embedded inside the hole that goes through the insulation film. This nesting allows the connection to be contained within a compact volume, achieving continuity without expanding the lateral footprint of the wiring pattern.
2Reliability
If the distance between division patterns is increased to reduce resistance, then conductivity is improved, but wiring pattern miniaturization becomes difficult
Solution Approach 1:
The invention reduces resistance by creating a vertical conductive path through the hole rather than relying solely on lateral connections. This 3D approach shortens the current path length and reduces resistance without requiring increased lateral spacing between division patterns.
Solution Approach 2:
The hole is formed in advance through the insulation film before the final wiring pattern is completed. This preliminary action creates a pre-established conductive pathway that simplifies subsequent wiring formation and ensures low resistance connection between division patterns.
3Area of stationary object
If dividing exposure is used to manufacture large-area semiconductor devices, then device area is increased, but alignment shift causes pattern discontinuity
Solution Approach 1:
The invention uses the vertical dimension (through the insulation film hole) to ensure pattern continuity across the boundary between adjacent regions. This 3D connection approach makes the continuity less sensitive to lateral alignment shifts that occur in dividing exposure processes.
Solution Approach 2:
The hole filled with conductor acts as an intermediary element that bridges the division patterns from adjacent regions. This mediator ensures electrical and physical continuity even when there are alignment shifts at the boundary between exposed regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables miniaturization of wiring patterns, improves yield and reliability by ensuring continuous conduction across regions, and suppresses the need for wider wiring intervals or multiple layers, thereby enhancing the pattern layout flexibility and reducing resistance values.
Implementation Method 1
first exposing for exposing a first portion of a photoresist arranged on the insulation film; second exposing for exposing a second portion of the photoresist after the first exposing
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method comprises arranging an insulator, forming a hole in the insulator, first exposing for exposing a first portion of a photoresist arranged on the insulator, second exposing for exposing a second portion of the photoresist, after the first and second exposing, forming a trench in the insulator in accordance with etching the insulator using a resist pattern formed by developing the photoresist as a mask and embedding a conductor in the hole and the trench. The trench includes a first trench corresponding to the exposure of the first portion of the resist pattern and a second trench corresponding to the exposure of the second portion of the resist pattern. The first and second trench each communicate with the hole and the hole is deeper than the first and second trench.