Semiconductor Wiring Hook-Up Asymmetry for Resistance Consistency
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Solution Overview
Problem
In semiconductor integrated circuit devices with multi-layer wiring structures, particularly in 3-D cell arrays, the existing via-contact structures face challenges in ensuring equal properties and reliability across multiple layers, leading to performance deterioration and disturbances in non-selected cells due to varying wiring resistances and alignment errors in hook-up areas.
Innovation Solution
The solution involves forming semiconductor integrated circuit devices with wiring hook-up portions of varying sizes and metal piece pairs with different space widths between layers, and burying contact conductors through interlayer insulating films to vertically lead wirings, ensuring consistent hook-up and reduced contact resistance across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via-contact structures are used in multi-layer wiring, then the device complexity is reduced, but the wiring resistance varies across layers and alignment errors occur
Solution Approach 1:
The patent applies local quality by making hook-up portions in different wiring layers have different sizes (widths and lengths) according to their specific positional requirements. This allows each layer's hook-up portions to be optimized for their local characteristics, ensuring consistent wiring resistance across all layers while maintaining reliable electrical connections.
Solution Approach 2:
The patent employs asymmetry by designing hook-up portions with different dimensions in different layers rather than using uniform symmetric structures. The first wiring layer has hook-up portions with specific width and length, while the second wiring layer has hook-up portions with different width and length, creating an asymmetric configuration that compensates for variations in wiring resistance and alignment across layers.
2Manufacturing precision
If uniform hook-up portions are used across all wiring layers, then the manufacturing process is simplified, but alignment errors and performance deterioration occur
Solution Approach 1:
The patent implements local quality by configuring hook-up portions with layer-specific dimensions. The first wiring layer's hook-up portions have optimized width and length for their position, while the second wiring layer's hook-up portions have different optimized dimensions. This local optimization improves alignment precision and reduces manufacturing errors without requiring complex multi-step fabrication processes.
3Reliability
If wiring hook-up portions have different sizes between layers, then wiring resistance consistency is improved, but the device complexity increases
Solution Approach 1:
The patent applies asymmetry by designing the hook-up portions in the first wiring layer with different width and length compared to the hook-up portions in the second wiring layer. This asymmetric configuration compensates for the cumulative effect of wiring resistance across layers, improving overall wiring performance stability while maintaining a relatively simple multi-layer wiring structure that is easy to manufacture.
Data Source
AI summary
A semiconductor integrated circuit device including: multiple wiring layers stacked on a semiconductor substrate with interlayer insulating films interposed therebetween; wiring hook-up portions extended from the corresponding wirings in the respective wiring layers; and contact conductors so buried in interlayer insulating films as to pass through the hook-up portions for vertically leading wirings of the respective wiring layers, wherein the hook-up portions have different sizes from each other between at least two layers in the wiring layers.