Semiconductor Wiring Impedance Matching via Conductor Chip Reference Plane
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Solution Overview
Problem
Increasing wiring density and signal lengths in semiconductor devices, particularly in SiP and PoP structures, lead to impedance mismatching issues, causing signal reflection and waveform distortion, especially with high-speed digital signals.
Innovation Solution
A semiconductor device configuration with a wiring board featuring a first region overlapping an electric conductor reference plane and a second region without overlap, where a conductor chip is mounted above the second region to function as the reference plane, ensuring consistent characteristic impedance across the wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wiring density is increased to support advanced semiconductor chip features and multi-chip structures, then the number of signal wirings and their lengths increase, but impedance matching becomes difficult to achieve over the whole length of the wiring
Solution Approach 1:
The wiring board is divided into multiple layers with power supply/ground layers alternately arranged. This segmentation creates multiple reference planes at different heights, allowing the wiring to maintain consistent characteristic impedance across different regions even as wiring density increases.
Solution Approach 2:
The invention transitions from a single-plane reference system to a multi-layer three-dimensional structure. By stacking power supply and ground layers at different heights, the system provides reference planes in multiple dimensions, enabling impedance control throughout the wiring length despite increased wiring density.
2Adaptability or versatility
If signal wiring length is increased to support multi-chip structures, then more chips can be integrated, but signal reflection and waveform distortion increase due to impedance mismatching
Solution Approach 1:
The multi-layer structure segments the electromagnetic field distribution, providing multiple reference planes along the signal path. This segmentation maintains impedance consistency even over long wiring lengths required for multi-chip configurations, reducing signal reflection and waveform distortion.
Solution Approach 2:
By changing the physical structure from single-layer to multi-layer configuration, the electrical parameters (impedance, capacitance, inductance) are optimized throughout the wiring length. This parameter optimization maintains signal integrity despite increased wiring length needed for multi-chip support.
3Manufacturing precision
If power supply/ground layers are provided inside the wiring board, then characteristic impedance can be formed, but the structure becomes more complex with multiple layers
Solution Approach 1:
The power supply and ground layers serve dual functions: they provide electrical power/grounding functions and simultaneously serve as reference planes for characteristic impedance formation. This multi-functionality reduces the need for separate reference plane structures, managing complexity while achieving impedance control.
Solution Approach 2:
The invention merges the power supply/grounding function with the reference plane function into the same layers. By combining these functions, the design avoids adding separate reference plane structures, thus achieving characteristic impedance formation without proportionally increasing structural complexity.
Data Source
AI summary
A semiconductor device has a wiring board having a wiring, a semiconductor chip that is mounted on the wiring board, and an electric conductor reference plane provided in the inside of the wiring board, in which in top view. The wiring includes a first region that overlaps the electric conductor reference plane and a second region that is the whole region except for the first region. A conductor chip is mounted above the second region.