Semiconductor Wiring Etching via Intermediate Layer
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Solution Overview
Problem
The existing methods for forming inter-substrate wiring in semiconductor apparatuses, such as CMOS image sensors, often result in connection failures due to insufficient etching of insulators and metal contamination from excessive etching of conductors, leading to reliability issues in electrical connections.
Innovation Solution
A manufacturing method involving a laminated body with specific insulator and conductor layers, where an intermediate layer with a different material is used between the insulator and conductor layers, and etching conditions are optimized to ensure the insulator is etched at a higher rate than the intermediate layer, allowing for stable formation of holes for conductive member formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If openings are made in the second groove and the third groove to the depths immediately in front of the aluminum wiring and the copper wiring, then the electrical connection between parts can be established, but a difference is generated between the thickness of remaining insulator to the aluminum wiring and the thickness of remaining insulator to the copper wiring, causing connection failure or damage to wiring
Solution Approach 1:
A third groove is introduced as an intermediary structure between the second groove (containing aluminum wiring) and the first groove (containing copper wiring). This third groove is filled with a resin layer that has different etching characteristics, serving as a buffer zone. When etching holes through this laminated structure, the resin layer in the third groove etches at a different rate than the insulator layers, creating a stepped etching profile that prevents both insufficient etching (connection failure) and excessive etching (wiring damage), thus resolving the precision-reliability contradiction
Solution Approach 2:
The single groove structure is segmented into three separate grooves (first, second, and third grooves) with different depths and filled materials. This segmentation allows each groove to be optimized for its specific function: the first groove for copper wiring connection, the second groove for aluminum wiring connection, and the third groove as a transition zone with resin filling. This segmentation enables controlled differential etching rates at different depths, solving the precision issue while maintaining connection reliability
2Reliability
If the bottoms of the second groove and the third groove are further removed by etching to expose the aluminum wiring and the copper wiring, then the electrical connection can be achieved, but excessive etching causes damage and metal contamination on the wiring
Solution Approach 1:
The third groove is pre-filled with resin material before the final etching process. This preliminary action creates a protective resin layer that covers the wiring surfaces. During the subsequent etching process to expose the aluminum and copper wirings, this pre-positioned resin layer acts as a protective barrier that prevents excessive etching from reaching and damaging the metal wiring, thereby preventing metal contamination while still allowing electrical connection to be established
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of electrical connections by preventing connection failures and reducing damage to the conductors, thereby improving the overall performance and reliability of the semiconductor apparatus.
Implementation Method 1
an etching condition of the first insulator layer when the first hole is formed is that an etching rate for the material of the first insulator layer under the etching condition is higher than an etching rate for the material of the intermediate layer under the etching condition
Data Source
AI summary
A first wiring part has an intermediate layer made of a material different from materials of a first insulator layer and a first conductor layer and located between the first insulator layer and the first conductor layer. In a step of forming a first hole, which penetrates through a first element part and the first insulator layer, from a side of a first semiconductor layer toward the first conductor layer, and forming a second hole, which penetrates through the first element part, the first wiring part, and a second insulator layer, from the side toward the second conductor layer, an etching condition of the first insulator layer when the first hole is formed is that an etching rate for the material of the first insulator layer under the etching condition is higher than an etching rate for the material of the intermediate layer under the etching condition.