Semiconductor Wiring Layer Etching for Dicing Integrity
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Solution Overview
Problem
Conventional BGA type semiconductor device manufacturing methods face issues with damage to the wiring layer during dicing due to stress and corrosion, and incomplete patterning of resist layers leading to reduced reliability.
Innovation Solution
A semiconductor device manufacturing method involving the formation of recesses along dicing lines, use of multiple resist layers for precise etching and patterning, and selective removal of the wiring layer to prevent damage and ensure accurate pattern formation, thereby improving the reliability of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the wiring layer is separated by dicing along the dicing line, then the semiconductor substrate can be divided into multiple semiconductor dice, but the wiring layer suffers damage such as peeling and corrosion due to stress and impact from the dicing blade
Solution Approach 1:
The wiring layer is selectively removed (taken out) from regions near the dicing line before the dicing process. This extraction prevents the wiring layer from being damaged during dicing, as the problematic portions are already removed. The patent achieves this by forming a resist pattern that covers the wiring layer in dicing line regions, then selectively etching away the wiring layer in those areas.
Solution Approach 2:
The wiring layer removal is performed as a preliminary action before the dicing process. By removing the wiring layer in advance in the regions that will be cut by the dicing blade, the patent prevents subsequent damage during dicing. This preliminary action ensures that when the dicing blade passes through, there is no wiring layer to cause peeling or corrosion issues.
2Device complexity
If a single resist layer is used for patterning the wiring layer, then the process is simpler, but light reflection from sidewalls causes incomplete removal of the resist layer and underlying wiring layer
Solution Approach 1:
The patterning process is segmented into multiple steps using multiple resist layers. The patent uses a first resist layer for initial patterning and a second resist layer for refined patterning. This segmentation allows each layer to perform a specific function, with the second layer correcting deficiencies from the first, ensuring complete and precise pattern formation without light reflection issues.
Solution Approach 2:
The patent adds another dimension to the patterning process by introducing a second resist layer on top of the first resist layer. This multi-layer approach in the vertical dimension allows light to be blocked from reaching sidewalls that would cause reflection, ensuring complete resist and wiring layer removal in the patterned regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents wiring layer damage during dicing and ensures complete patterning, enhancing the reliability and accuracy of semiconductor device separation without the issues of peeling or corrosion, thus improving the overall performance of the semiconductor device.
Implementation Method 1
forming a recess in the substrate along a dicing line of the substrate by etching the substrate from a back surface thereof
Data Source
AI summary
The invention is directed to improvement of reliability of a process of separating a layer to be patterned such as a wiring layer in a semiconductor device manufacturing method. A wiring layer is formed on a back surface of a semiconductor substrate. A third resist layer (positive resist layer) is formed on the wiring layer, having an opening in a predetermined region along a dicing line at a bottom of the opening, and the wiring layer is etched using the third resist layer as a mask. After the third resist layer is removed, a fourth resist layer (negative resist layer) is formed on the wiring layer so as to leave the wiring layer in a region of a predetermined pattern, and the wiring layer is etched using the fourth resist layer as a mask. The wiring layer is thus patterned so as to form the predetermined pattern and be separated at the predetermined region along the dicing line at the bottom of the opening without fail.