Semiconductor Device Wiring Layer Routing Method
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Solution Overview
Problem
The increasing complexity of semiconductor design rules and reduced pitch in semiconductor fabrication processes complicate the routing process for wiring layer design, particularly in layout design and integration of complex semiconductor devices.
Innovation Solution
A semiconductor device structure and manufacturing method that includes specific active patterns, gate electrodes, lower and upper wiring layers, and vias, where upper wiring patterns are connected to specific upper vias without connecting to others, allowing for improved routing efficiency and reduced design complexity by predesignating pin regions and using a cell library to simplify the routing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch between adjacent patterns is reduced to increase integration, then the device density is improved, but the routing process complexity increases
Solution Approach 1:
The patent segments the routing process into two distinct directions: lower wiring patterns route signals in a first direction (e.g., east-west), while upper wiring patterns route signals in a second direction (e.g., north-south) perpendicular to the first direction. This segmentation of routing directions simplifies the overall routing complexity by eliminating the need for complex multi-directional routing calculations, thereby enabling higher device density without proportionally increasing routing process complexity.
2Quantity of substance
If the standard cell height is reduced to increase integration, then the device density is improved, but the design rule complexity increases
Solution Approach 1:
The patent applies local quality by assigning different routing direction requirements to different layers of the wiring structure. Specifically, lower wiring patterns are designated to extend in a first direction while upper wiring patterns extend in a second direction perpendicular thereto. This localized differentiation of routing characteristics simplifies design rule verification and reduces overall design rule complexity, enabling reduced standard cell heights and increased device density.
3Adaptability or versatility
If complex wiring layer design is performed without predesignated pin regions, then the design flexibility is maintained, but the routing process runtime increases
Solution Approach 1:
The patent implements preliminary action by predesignating specific pin regions in the lower wiring patterns before the actual routing process begins. These predesignated pin regions serve as predetermined connection points that guide the routing of upper wiring patterns. This preliminary designation reduces the computational search space during routing, significantly decreasing routing process runtime while maintaining design flexibility through the ability to strategically place these predesignated regions.
Data Source
AI summary
A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction. The first upper wiring pattern is connected to the first upper via without being connected to the second upper via and the second upper wiring pattern is connected to the second upper via without being connected to the first upper via.