Semiconductor Device Wiring Layout for Inductance Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing inductance to achieve high-speed switching operations, as existing designs do not effectively minimize inductance generated in the device.
Innovation Solution
The semiconductor device incorporates a configuration with first and second semiconductor elements, insulating base members, and wiring members, where the wiring members face each other and are electrically connected, allowing current to flow in opposite directions through them, thereby reducing inductance by minimizing the distance between parallel reciprocating conducting lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wiring layouts are used with larger placement margins, then manufacturing ease and reliability are improved, but inductance increases and switching speed decreases
Solution Approach 1:
The patent transitions from planar wiring layouts to a three-dimensional configuration where wiring members extend in the thickness direction of the insulating base member. This vertical arrangement allows parallel reciprocating conducting lines to face each other with minimal distance, reducing inductance while maintaining compact footprint and enabling high-speed switching operations
2Object-generated harmful factors
If wiring members are placed closer together to reduce inductance, then switching speed improves, but positional accuracy requirements increase and manufacturing difficulty increases
Solution Approach 1:
The patent divides the wiring structure into multiple segments: wiring members extending in the thickness direction, face-to-face wiring members on opposite surfaces, and connection portions within the insulating base member. This segmentation allows each component to be optimized independently while maintaining overall compactness and reducing inductance without excessive precision requirements
Solution Approach 2:
The wiring members are nested within the insulating base member structure, with connection portions embedded in the base member material. This nesting approach allows wiring members to be positioned closely together in the thickness direction while the insulating base member provides structural support and electrical isolation, reducing inductance without requiring extreme positional precision
Data Source
Figure 1
Figure 2
Figure 3A~3C
AI summary
A semiconductor device includes: a first semiconductor element (10); a second semiconductor element (20); a first insulating base member (41) including a fifth face (41A) and a sixth face (41B); a second insulating base member (81) including a seventh face (81A) and an eighth face (81B); a first wiring (61) that penetrates through the first insulating base member (41), and disposed on the sixth face (41B); a second wiring (62) that penetrates through the second insulating base member (81), and disposed on the eighth face (81B); a first wiring member (110, 210) that faces a second face (10B) of the first semiconductor element (10); and a second wiring member (120) that is provided on the second wiring (62). The first wiring member (110, 210) is provided on the seventh face of the second insulating base member. A current flows in a first direction in the first wiring member (110, 210), and flows in a second direction opposite to the first direction in the second wiring member (120).