Semiconductor Device Wiring Layout for Noise Reduction
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Solution Overview
Problem
Semiconductor devices face challenges in optimizing the layout and performance characteristics due to the restricted shape and size of substrates, leading to inefficiencies in connecting nonvolatile semiconductor memory elements and controllers, which affects the overall performance and stability of the devices.
Innovation Solution
A semiconductor device configuration with a multi-layered substrate featuring a specific arrangement of nonvolatile NAND memories, a drive control circuit, DRAM, and resistive elements, where the NAND memories are aligned along the longitudinal direction of the substrate, and resistive elements are strategically placed to balance wiring lengths and reduce noise interference, enhancing performance and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If nonvolatile semiconductor memory elements and controllers are disposed on a substrate with restricted shape and size, then the device can meet specification requirements, but the wiring length increases and noise interference worsens
Solution Approach 1:
The patent utilizes multi-layered substrate structure to route signals in three dimensions. Control lines are distributed across multiple layers (first through fourth layers) with different orientations, allowing signals to reach memory elements without excessive length while maintaining compact footprint on the substrate.
Solution Approach 2:
The substrate is divided into multiple functional layers, each handling specific signal routing tasks. The control lines are segmented across different layers and orientations, with first control lines on one layer and second control lines on another, reducing mutual interference and optimizing individual path lengths.
2Area of stationary object
If components are densely packed to optimize substrate usage, then area efficiency improves, but wiring complexity and noise interference increase
Solution Approach 1:
By extending wiring into the vertical dimension with multiple substrate layers, the patent achieves compact horizontal layout while maintaining manageable wiring complexity. The multi-layer approach allows parallel routing without excessive planar density.
Solution Approach 2:
The patent employs asymmetric wiring patterns where first control lines extend in one direction and second control lines extend in another direction. This asymmetric arrangement optimizes routing efficiency for different signal types while preventing uniform complexity distribution.
3Reliability
If wiring patterns are extended to connect distant components, then connectivity is achieved, but wiring length increases causing performance deterioration
Solution Approach 1:
The patent routes control lines through multiple substrate layers to create more direct three-dimensional paths between controllers and memory elements. This reduces the effective wiring length compared to surface-only routing while ensuring reliable connections.
Solution Approach 2:
The wiring pattern is dynamically optimized with control lines extending in different directions on different layers. First control lines extend in a first direction on a first layer, while second control lines extend in a second direction on a second layer, adapting the path to minimize length for each specific connection.
Data Source
AI summary
According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.