Semiconductor Device Wiring Layout for Parasitic Resistance Reduction
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Solution Overview
Problem
There is a need to reduce the on-resistance in semiconductor devices, particularly in transistors, which includes components from both the transistor itself and the wiring, as existing technologies have not effectively addressed this issue.
Innovation Solution
The semiconductor device configuration includes multiple transistor units arranged side by side with specific wiring patterns where first and second wiring extend between units, and third and fourth wiring are coupled to source and drain electrodes, respectively, reducing parasitic resistance by optimizing wiring layout and integration with transistor electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transistor cells are arranged in parallel with drain and source wiring pulled out from each transistor, then the transistor configuration can be established, but the wiring resistance component increases
Solution Approach 1:
The patent merges the drain wiring and source wiring into a single wiring structure that serves both functions. Instead of having separate drain and source wiring pulled out from each transistor, a unified wiring structure is created that reduces the total wiring resistance while maintaining the parallel transistor configuration.
Solution Approach 2:
The patent transitions from a planar wiring arrangement to a three-dimensional stacked configuration. Transistor units are arranged in multiple layers with wiring extending in different spatial dimensions, allowing for optimized current paths that reduce wiring resistance while maintaining compact device geometry.
2Adaptability or versatility
If wiring is extended to connect multiple transistor units, then device functionality is achieved, but parasitic resistance increases
Solution Approach 1:
The unified wiring structure serves multiple functions simultaneously: it acts as both drain and source wiring for different transistor units, provides electrical connection across multiple layers, and minimizes parasitic resistance through its optimized geometry. This multi-functional design reduces the overall parasitic resistance while maintaining full device functionality.
Data Source
AI summary
Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.