Semiconductor Wiring Loop Ends for Trailing Suppression
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Solution Overview
Problem
The trailing phenomenon in semiconductor storage device wiring layers leads to narrower wiring intervals, increasing the risk of breakdown voltage reduction and short circuits due to wider lower parts of wirings compared to upper parts, especially at end points with low wiring density and irregularity.
Innovation Solution
A wiring structure where the end of the second wiring is formed into one or more loops, increasing wiring density and regularity at the end points, thereby preventing the trailing phenomenon and reducing the likelihood of breakdown voltage reduction and short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring intervals are narrowed to increase device integration, then productivity and device density are improved, but the trailing phenomenon causes breakdown voltage reduction and short circuit risk increases
Solution Approach 1:
The patent applies local quality by modifying only the end portions of wirings to form loops, while keeping the main body of the wiring structure unchanged. This localized modification increases wiring density and regularity specifically at end points where the trailing phenomenon occurs, without altering the overall wiring interval design that enables high device density.
Solution Approach 2:
The patent employs curvature by forming loop structures at the end portions of wirings. These loops create a curved geometry that increases the effective path length and wiring density at critical end points, thereby mitigating the trailing phenomenon and preventing short circuits while maintaining the linear structure needed for high-density integration.
2Reliability
If wiring end points are modified to prevent trailing phenomenon, then reliability is improved, but wiring structure complexity increases
Solution Approach 1:
The patent segments the wiring structure by distinguishing between the main body portion and the end portions of wirings. Only the end portions are modified to form loops, while the main body remains unchanged. This segmentation allows the reliability improvement to be achieved with minimal additional complexity, as the modification is confined to specific locations rather than the entire wiring network.
3Manufacturing precision
If loops are formed at wiring ends to increase wiring density, then trailing phenomenon is reduced, but parasitic capacitance may increase
Solution Approach 1:
The patent applies partial action by forming loops only at the end portions of wirings where the trailing phenomenon occurs, rather than modifying the entire wiring structure. This partial modification achieves the necessary wiring density and regularity improvement at critical locations while minimizing the total area occupied by loop structures, thereby limiting the increase in parasitic capacitance to the minimum necessary level.
Data Source
AI summary
A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.