Semiconductor Wiring Loop Layout to Prevent End-Point Trailing
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Solution Overview
Problem
The trailing phenomenon in semiconductor storage device wiring layers leads to narrower wiring intervals, increasing the risk of breakdown voltage reduction and short circuits due to wider lower parts of wirings compared to upper parts, especially at end points with low wiring density and irregularity.
Innovation Solution
A wiring structure where the end of the second wiring is formed into one or more loops, increasing wiring density and regularity at the end points, preventing the trailing phenomenon and reducing the likelihood of breakdown voltage reduction and short circuits by maintaining a consistent width and avoiding close proximity to adjacent wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring intervals are narrowed to increase integration density, then productivity and device capacity improve, but the trailing phenomenon causes breakdown voltage reduction and short circuit risks
Solution Approach 1:
The patent applies local quality by modifying only the end portions of wirings with loop formations, while keeping the main body of wirings straight and maintaining original wiring intervals. This localized modification increases wiring density and regularity specifically at end points where trailing phenomenon occurs, without affecting the overall wiring structure or requiring changes to the entire wiring layer, thus improving integration density while preventing short circuits.
Solution Approach 2:
The patent uses curvature by forming loops at the end portions of wirings, transforming straight-line geometry into curved configurations. These loops increase the effective length of wirings without increasing the bounding box area, thereby improving integration density. The curved loop structures also prevent the trailing phenomenon by creating a more regular wiring pattern that maintains consistent breakdown voltage.
2Area of stationary object
If wiring intervals are reduced, then area utilization improves, but parasitic capacitance increases due to closer proximity of wirings
Solution Approach 1:
The patent segments the wiring structure by adding loop formations at end portions, effectively dividing the continuous wiring into sections with increased path length. This segmentation allows the wiring to occupy more space within the same bounding box, improving area utilization without requiring the wiring to be placed closer to adjacent wirings, thereby avoiding increased parasitic capacitance.
3Manufacturing precision
If wiring density is increased at end points, then trailing phenomenon is prevented, but manufacturing complexity increases
Solution Approach 1:
The patent applies partial action by implementing loop formations only at the end portions of wirings where trailing phenomenon occurs, rather than modifying the entire wiring structure. This selective approach achieves the necessary increase in wiring density and regularity at critical locations without unnecessarily complicating the overall wiring design, thus improving manufacturing precision while minimizing device complexity.
Data Source
AI summary
A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.