Semiconductor Wiring Layout for Low-Inductance Power Conversion
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Solution Overview
Problem
Conventional semiconductor devices for power conversion experience high parasitic inductance due to stacked printed circuit boards, leading to surge voltages that can destroy semiconductor elements during high-speed switching operations.
Innovation Solution
A semiconductor device design featuring a substrate with intersecting wiring groups, where the direction of current flow through specific connection parts within the substrate cancels magnetic flux, reducing parasitic inductance and enhancing reliability during high-speed switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If stacked printed circuit boards are used to connect electrodes to semiconductor elements, then wiring inductance is reduced, but parasitic inductance increases due to multiple board layers
Solution Approach 1:
The patent merges the connection functions of multiple printed circuit boards into a single substrate that contains all wiring groups (first through fourth wiring groups) and connection parts (first connection part and second connection part) integrated within one structure. This eliminates the need for stacking multiple boards while providing all necessary electrical connections between electrodes and semiconductor elements.
Solution Approach 2:
The patent transitions from a planar multi-layer PCB structure to a three-dimensional wiring configuration within a single substrate. The wiring groups extend in multiple directions (first direction and second direction intersecting at the first surface) and the connection parts extend in a direction intersecting the first surface, creating a spatial arrangement that reduces current path length and parasitic inductance.
2Reliability
If current flows through multiple board layers, then electrical connection is achieved, but surge voltage exceeds withstand voltage and destroys semiconductor elements
Solution Approach 1:
The patent designs the wiring groups and connection parts in advance to minimize current path length and optimize current distribution. The first wiring group connects the first electrode to the first semiconductor element, the second wiring group connects the first semiconductor element to the second electrode, the third wiring group connects the third electrode to the second semiconductor element, and the fourth wiring group connects the second semiconductor element to the second electrode, all within the single substrate before assembly.
Solution Approach 2:
The patent changes the physical parameters of the wiring structure by reducing the length and number of wiring paths compared to stacked PCB designs. The wiring groups are configured to minimize inductance by optimizing their geometry and arrangement within the substrate, thereby reducing the magnitude of surge voltages generated during high-speed switching operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces parasitic inductance and ensures high reliability of semiconductor devices even during high-speed switching operations by canceling magnetic flux, preventing damage from surge voltages.
Implementation Method 1
When a voltage is applied between the first electrode and the third electrode to cause current to flow through the second electrode, a direction of current flowing through the first connection part is opposite to a direction of current flowing through the second connection part
Data Source
AI summary
A semiconductor device includes a substrate having a first surface, a first electrode, a second electrode and a third electrode formed on the first surface, a first semiconductor element and a second semiconductor element disposed in the interior of the substrate, a first wiring group electrically connecting the first electrode to the first semiconductor element, and a fourth wiring group electrically connecting the second semiconductor element to the second electrode. The first wiring group includes a first connection part disposed in the interior of the substrate. The fourth wiring group includes a second connection part disposed in the interior of the substrate. When a voltage is applied between the first electrode and the third electrode to cause current to flow through the second electrode, a direction of current flowing through first connection part is opposite to a direction of current flowing through the second connection part.