Semiconductor Module Wiring Layout for Low Inductance and Downsizing
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Solution Overview
Problem
Existing semiconductor devices face challenges in miniaturization due to low layout freedom and high wiring inductance, particularly in power semiconductor modules where the first and second wiring layers must be vertically opposite, limiting device downsizing.
Innovation Solution
A semiconductor device design that includes an insulating layer, a foil conductor, a circuit pattern, and multiple semiconductor elements, where the wiring boards are not vertically opposite, allowing for a current path with lower electrical resistance on the downstream side, enhancing inductance cancellation through magnetic flux from the foil conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the first wiring layer and the second wiring layer are arranged vertically opposite to reduce wiring inductance, then the wiring inductance is reduced, but the layout freedom is limited and device miniaturization becomes difficult
Solution Approach 1:
The patent applies asymmetry by arranging the first and second wiring layers in a planar configuration rather than vertically opposite symmetric arrangement. The wiring layers are positioned at different heights and locations on the same substrate plane, breaking the traditional symmetric vertical opposition to achieve both inductance reduction and layout flexibility.
Solution Approach 2:
The patent transitions from a two-dimensional vertical opposite arrangement to a three-dimensional planar arrangement with varying heights. The wiring layers are positioned at different Z-heights on the same substrate plane, utilizing the third dimension (height) to achieve inductance reduction while maintaining layout freedom in the XY plane.
2Object-affected harmful factors
If the wiring layers are arranged vertically opposite to reduce inductance, then the inductance canceling effect is achieved, but the device size cannot be reduced
Solution Approach 1:
The patent utilizes the Z-dimension (height) to position wiring layers at different levels on the same substrate plane, rather than requiring vertical opposition. This dimensional approach allows the wiring to achieve inductance cancellation through controlled current paths while maintaining a compact planar footprint, enabling device miniaturization.
Solution Approach 2:
The patent segments the current path into multiple sections with different wiring layers positioned at different heights. By dividing the current flow into segments that traverse different Z-levels, the design achieves inductance reduction through distributed magnetic flux cancellation while maintaining compact overall device dimensions.
3Object-affected harmful factors
If the current path is designed to flow through multiple semiconductor elements with varying resistance, then more current flows through downstream elements closer to the foil conductor, but the circuit design becomes more complex
Solution Approach 1:
The patent applies local quality by creating non-uniform current distribution through varying semiconductor element resistances along the current path. Each semiconductor element is designed with specific resistance characteristics that locally control current flow, causing more current to naturally flow through downstream elements closer to the foil conductor, thereby enhancing inductance cancellation in critical regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves both downsizing and reduced wiring inductance by securing layout freedom and increasing the inductance canceling effect, with more current flowing through semiconductor elements closer to the foil conductor, thereby reducing overall inductance.
Implementation Method 1
the inductance canceling effect due to the magnetic flux formed by the foil conductor increases
Implementation Method 2
the inductance canceling effect due to the magnetic flux formed by the foil conductor increases
Data Source
AI summary
A semiconductor device includes an insulating layer; a foil conductor, a circuit pattern, a plurality of semiconductor elements, a first wiring board allowing an externally input current to flow through the circuit pattern, and a wiring board connecting the plurality of semiconductor elements and allowing the current that flowed through the plurality of semiconductor elements via the circuit pattern to flow. The plurality of semiconductor elements are arranged along an extending direction of the wiring board and, in a current path passing from the wiring board through the wiring board via the circuit pattern and the plurality of semiconductor elements, the electrical resistance of the current path passing through the semiconductor element arranged on the downstream side is lower than the electrical resistance of the current path passing through the semiconductor element arranged on the upstream side.