Semiconductor Wiring Modeling for Signal Delay Accuracy
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Solution Overview
Problem
Existing semiconductor device design methods inaccurately estimate signal delays due to discrepancies between manufacturing aims and actual wiring cross-sectional profiles, leading to errors in wiring capacitance and resistance calculations, which can cause operational issues in semiconductor chips.
Innovation Solution
A wiring modeling technique that involves selecting a region on a semiconductor device, calculating the wiring area ratio, and determining the cross-sectional profile of target wirings to accurately model and predict wiring resistance and capacitance, incorporating test patterns with varying parameters to account for wiring width, spacing, and layout conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If prior wiring capacitance and wiring resistance estimation methods are used assuming all wirings are formed according to the manufacturing aim, then the calculation process is simple, but the signal delay estimation contains errors leading to potential chip operation failures
Solution Approach 1:
The invention changes the parameters used for wiring estimation from ideal manufacturing aim dimensions to actual formed dimensions that reflect real cross-sectional profiles. By using measured or simulated actual wiring dimensions including variations in width, thickness, and shape, the estimation accurately captures real signal delay characteristics while maintaining calculation feasibility through parameter substitution.
Solution Approach 2:
The invention introduces feedback by using actual formed wiring cross-sectional profiles (obtained through measurement or simulation) to correct the estimation model. This feedback loop ensures that the capacitance and resistance calculations reflect real manufacturing variations, preventing chip operation failures while maintaining a systematic calculation approach.
2Device complexity
If the cross-sectional profile for wiring capacitance estimation is assumed identical to that for wiring resistance estimation, then the modeling process is simplified, but the estimation accuracy deteriorates because capacitance and resistance depend on different geometric factors
Solution Approach 1:
The invention segments the wiring estimation process into two independent parts: one for capacitance estimation and one for resistance estimation. Each part uses its own appropriate cross-sectional profile parameters - capacitance uses profiles reflecting surface area for electric field calculations, while resistance uses profiles reflecting conductive cross-section area. This segmentation eliminates the error of assuming identical profiles while keeping each sub-model relatively simple.
Solution Approach 2:
The invention applies local quality by using different cross-sectional profile characteristics for different estimation purposes. The capacitance estimation uses profile parameters optimized for electric field distribution (such as surface area and shape factors), while resistance estimation uses parameters optimized for current flow (such as conductive cross-section area and path length). Each local estimation uses the quality most appropriate for its specific physical phenomenon.
3Ease of operation
If manufacturing aim dimensions are used for wiring estimation, then the design process is straightforward, but the discrepancy between aim and actual profile increases with finer wirings leading to larger estimation errors
Solution Approach 1:
The invention performs preliminary action by obtaining or simulating the actual formed wiring cross-sectional profiles before conducting capacitance and resistance estimations. This preliminary step captures manufacturing variations and profile characteristics that will actually exist on the chip, allowing subsequent calculations to be based on realistic dimensions rather than ideal target dimensions, thereby improving accuracy without complicating the overall design workflow.
Data Source
AI summary
In a semiconductor device having wirings, a wiring modeling technique according to the present invention comprises the steps of selecting an arbitrary region of the semiconductor device; calculating a wiring area ratio of the wirings to the region; and determining the region and the wiring area ratio to model the cross-sectional profile of a target wiring located in the middle of the region.