Semiconductor Wiring Patterning With Multi-Layer Masks at Tight Pitch
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Solution Overview
Problem
The reliability of wiring patterns in semiconductor devices is compromised due to the decreasing pitch between circuit components, necessitating improved fabrication methods to enhance their integrity.
Innovation Solution
A method involving the sequential formation of insulating and mask material layers, followed by the creation of middle mask patterns, spacer and sacrificial patterns, and controlled etching processes to form wiring patterns with specific orientations and spacings, ensuring reliable separation and reduced edge curvature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch between wiring patterns is decreased to achieve higher integration, then the device density increases, but the reliability of wiring patterns deteriorates due to increased edge curvature and reduced separation
Solution Approach 1:
The patent divides the mask formation process into multiple stages with different mask materials (first mask material layer and second mask material layer) and uses multiple etching processes with different etchants. This segmentation allows selective removal of materials to achieve straight wiring edges while maintaining small pitch, resolving the contradiction between high integration and wiring reliability.
Solution Approach 2:
The patent introduces a vertical dimension by forming mask patterns with multiple layers at different heights and using spacer structures. The first and second mask material layers are formed at different vertical positions, and etching proceeds from upper to lower layers, enabling precise lateral patterning that produces straight wiring edges even at reduced pitch.
2Ease of manufacture
If conventional single-layer mask etching is used, then the manufacturing process is simple, but the wiring patterns exhibit excessive edge curvature reducing reliability
Solution Approach 1:
The mask formation is segmented into multiple layers (first mask material layer and second mask material layer) that are etched sequentially using different etchants. This multi-layer approach replaces the conventional single-layer mask process, achieving straight wiring edges through controlled selective etching while maintaining manufacturing feasibility.
Solution Approach 2:
The patent uses a spacer structure as an intermediary element between the mask patterns and the final wiring structure. The spacer is formed conformally on the mask patterns and then etched back, serving as a mediator that defines the final wiring width and ensures straight edges. This intermediary step enables precise patterning without requiring direct etching of the wiring layer from the mask.
3Manufacturing precision
If multiple etching processes with different etchants are used, then wiring edge straightness is improved, but the manufacturing complexity increases
Solution Approach 1:
The etching process is segmented into multiple selective etching steps, each using a specific etchant that reacts with a particular mask material layer. The first etchant selectively etches the first mask material layer, while the second etchant selectively etches the second mask material layer. This segmentation enables precise control over wiring edge geometry, achieving straight edges through controlled material removal at each stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability of wiring patterns by minimizing edge curvature and improving the separation between adjacent patterns, thereby reducing the risk of defects and enhancing overall device performance.
Implementation Method 1
forming a first photoresist pattern having a first hole pattern on an upper surface of the first upper mask material layer
Implementation Method 2
etching the first upper mask material layer through the first hole pattern to form a first trench exposing a portion of the spacer material layer
Implementation Method 3
conformally forming a spacer material layer on each of the upper surface of the lower mask material layer, a sidewall and an upper surface of the first middle mask pattern
Data Source
AI summary
A method for fabricating a semiconductor device includes sequentially forming an insulating material layer and a lower mask material layer on an upper surface of the substrate, forming first and second middle mask patterns on an upper surface of the lower mask material layer forming a spacer material layer on the upper surface of the lower mask material layer, a sidewall and an upper surface of the first middle mask pattern, and a sidewall and an upper surface of the second middle mask pattern, forming a first upper mask material layer on an upper surface of the spacer material layer, forming a first photoresist pattern having a first hole pattern on an upper surface of the first upper mask material layer for exposing a portion of the first upper mask material layer between the first and second middle mask patterns.