Semiconductor Wiring Structure via Multi-Mask Etching

The patent divides a single via hole into multiple via holes (first via holes and second via holes) with different densities. The first via holes are formed with lower density at specific positions, while the second via holes are formed with higher density at other positions. This segmentation allows the wiring to contact multiple via holes, increasing the total contact area and reducing contact resistance while maintaining via hole size reduction for circuit density.

The patent applies different via hole densities at different locations beneath the wiring. Specifically, first via holes with lower density are positioned at certain regions, while second via holes with higher density are positioned at other regions. This local variation in via hole density optimizes the contact area between wiring and vias in different areas, reducing overall contact resistance while maintaining via hole size reduction for circuit density.

The patent segments the via hole formation into two distinct groups: first via holes formed with lower density and second via holes formed with higher density. This segmentation strategy allows the overall via structure to maintain adequate contact area with the wiring while enabling individual via holes to be smaller in size, thus resolving the contradiction between via hole size reduction and contact resistance increase.

The patent implements local quality variation by forming first via holes with lower density at specific positions and second via holes with higher density at other positions beneath the wiring. This localized differentiation in via hole density ensures that the total contact area between wiring and vias is sufficient to maintain low contact resistance, while still allowing via hole size reduction for improved circuit density.