Semiconductor Device Wiring Arrangement for Narrow Frame Design
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Solution Overview
Problem
Existing display devices face challenges in achieving a narrower frame region while maintaining circuit characteristics, leading to degraded display image quality due to reduced wiring widths in peripheral circuits.
Innovation Solution
A semiconductor device with a specific wiring arrangement, including main and bifurcation wiring sections, and transistors divided into pieces, where branch wiring sections function as gate electrodes, allowing for efficient arrangement and reduced wiring width, thereby achieving space saving without degrading characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wiring width within peripheral circuit is reduced to achieve narrower frame, then frame area is reduced, but circuit characteristics and display image quality are degraded
Solution Approach 1:
The transistor gate electrode is divided into multiple segments (first gate electrode and second gate electrode) arranged in a stacked configuration. This segmentation allows the gate to control multiple source and drain regions, effectively increasing the transistor's current handling capacity without increasing the lateral wiring width, thus maintaining circuit characteristics while enabling narrower frame design
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional stacked gate structure. By arranging gate electrodes vertically (in the thickness direction) rather than only laterally, the design utilizes the third dimension to increase functional density, allowing narrower wiring width while maintaining or improving circuit characteristics
2Area of stationary object
If wiring width within peripheral circuit is reduced to achieve space saving, then area is reduced, but display image quality is lowered due to flicker phenomenon
Solution Approach 1:
The gate electrode is segmented into multiple parts (first and second gate electrodes) that can independently control different transistor channels. This segmentation enables better current distribution and reduces hot carrier effects, suppressing flicker phenomenon while maintaining compact area
Solution Approach 2:
Multiple source and drain regions are merged into a single transistor structure controlled by the stacked gate. This merging increases the effective channel width without increasing lateral footprint, reducing flicker by distributing current across multiple channels while saving space
Data Source
AI summary
A semiconductor device including: one or more pieces of first wiring having a main wiring section and a bifurcation wiring section; one or a plurality of pieces of second wiring having a trunk wiring section and a plurality of branch wiring sections within a gap region between the main wiring section and the bifurcation wiring section; one or a plurality of transistors each divided and formed into a plurality of pieces, the plurality of branch wiring sections individually functioning as a gate electrode and the one or plurality of transistors having a source region formed within the main wiring section and within the bifurcation wiring section and having a drain region formed between the plurality of branch wiring sections; and one or a plurality of pieces of third wiring electrically connected to the drain region of the one or plurality of transistors.