Semiconductor Wiring Layout With Openings for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing parasitic capacitance between wirings, particularly in light emitting devices, where forming a cavity in the insulation film is difficult, leading to increased capacitance and potential interference with device performance.
Innovation Solution
The semiconductor device incorporates a configuration with upper and lower wirings connected via an insulation film, where specific openings are strategically placed to reduce parasitic capacitance, allowing for easier current flow and magnetic field cancellation, and utilizing substrates with different materials like silicon and gallium arsenide to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a cavity is provided in the insulation film to reduce parasitic capacitance, then parasitic capacitance between wirings is reduced, but manufacturing complexity increases due to difficulty in forming the cavity
Solution Approach 1:
The patent extracts the harmful insulating material from between the lower and upper wirings by providing openings that extend from the front surface to the back surface of the substrate. This removes the dielectric material that causes parasitic capacitance, allowing the harmful factor (insulation film) to be taken out from the critical region between wirings while maintaining insulation where needed.
Solution Approach 2:
The patent creates a porous structure in the substrate by forming openings that penetrate through it. These openings create air gaps or voids between the lower and upper wirings, effectively reducing parasitic capacitance. The substrate transitions from a solid insulating structure to a porous one in the regions where capacitance reduction is needed.
2Object-affected harmful factors
If openings are provided in wirings to reduce parasitic capacitance, then parasitic capacitance is reduced, but current flow path is interrupted
Solution Approach 1:
The patent segments the wirings into multiple parts separated by openings. The lower wiring and upper wiring are divided into segments with gaps between them. This segmentation reduces the overlapping area between wirings, thereby reducing parasitic capacitance, while the wirings remain electrically functional through their segmented structure.
Solution Approach 2:
The patent resolves the current flow interruption issue by extending openings in specific directions (first direction and second direction) that are perpendicular to the current flow direction. This dimensional arrangement ensures that openings reduce capacitance between adjacent wirings without blocking the current path along the wiring length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, improves current flow, and cancels magnetic fields, leading to enhanced device accuracy and efficiency, particularly in light emitting devices used for distance measurement applications.
Implementation Method 1
it is possible to easily reduce parasitic capacitance between the wirings by providing the first opening in the lower wiring or between the lower wirings
Implementation Method 2
the lower wiring may be used such that current flows in the first direction, and the upper wirings may be used such that current flows in a direction opposite to the first direction. Hence, for example, it is possible to cause a magnetic field generated around the upper wirings and a magnetic field generated around the lower wiring to cancel each other out
Data Source
AI summary
Provided is a semiconductor device capable of easily reducing parasitic capacitance between wirings.A semiconductor device according to the present disclosure includes a first substrate, a lower wiring provided on the first substrate, a plurality of upper wirings provided on the lower wiring via an insulation film, and a second substrate provided on the upper wirings via a plurality of elements, in which the upper wirings include a first wiring and a second wiring adjacent to each other in a first direction, the elements on the first wiring and the elements on the second wiring are connected in series to each other, and a first opening is provided in the lower wiring or provided so as to be sandwiched between the lower wirings in a second direction different from the first direction, or a second opening is provided in the upper wirings or provided so as to be sandwiched between the upper wirings in the second direction.