Semiconductor Wiring Pad Structure for Reliable Low-Cost Packaging
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved reliability and electrical properties while maintaining reduced manufacturing costs through process simplification.
Innovation Solution
A semiconductor package design featuring a substrate with a seed layer, a wiring pad with a pad portion and a capping layer, and a method of fabrication that includes forming a resist pattern, creating spacer patterns, forming the pad portion, removing spacers, and depositing the capping layer, all performed in a simplified photolithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional pad fabrication processes are used, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the pad formation process with the via hole formation process into a single photolithography step. The resist pattern serves dual purposes: defining via holes and defining pad regions. This merging of functions reduces the number of separate fabrication steps, simplifying the overall manufacturing process while maintaining pad structure precision
Solution Approach 2:
The resist pattern performs multiple functions simultaneously: it acts as an etch mask for via holes, defines pad boundaries, and serves as a template for subsequent pad material deposition. This multi-functionality eliminates the need for separate patterning steps, reducing process complexity and manufacturing cost
2Reliability
If conventional pad structures are used, then manufacturing process can be simple, but reliability and electrical properties deteriorate
Solution Approach 1:
The pad structure employs an asymmetric tapered geometry where the top surface width differs from the bottom surface width. This asymmetric design improves stress distribution and mechanical reliability of the pad connection while enhancing electrical properties through optimized current flow paths. The tapered shape is achieved through controlled etching that creates different widths at top and bottom surfaces
Solution Approach 2:
The pad structure features different dimensions at different locations - the top surface has a different width than the bottom surface. This local variation in geometry optimizes both mechanical attachment quality and electrical conductivity locally, improving overall reliability without requiring complex multi-material constructions
3Reliability
If additional fabrication steps are added to improve pad properties, then reliability improves, but productivity decreases
Solution Approach 1:
The patent merges pad patterning with via hole patterning into a single photolithography exposure and development step. The same resist pattern defines both features, eliminating sequential processing steps. This merging maintains improved pad electrical properties through precise geometry control while significantly increasing fabrication productivity by reducing process time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the reliability and electrical properties of semiconductor packages while simplifying the fabrication process, thereby reducing manufacturing costs and improving fabrication speed.
Implementation Method 1
forming a seed layer on a substrate
Implementation Method 2
forming a capping layer that fills the through hole and covers a top surface and the lateral surface of the pad portion
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate, a seed layer on the substrate, and a wiring pad on the seed layer. The wiring pad includes a pad portion, and a capping layer on the seed layer and covering a top surface and a lateral surface of the pad portion. A bottom surface of the pad portion is in contact with a top surface of the seed layer. A width of the top surface of the pad portion is greater than a width of the bottom surface of the pad portion.