Semiconductor Wiring Insulation Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Active matrix liquid crystal display devices face challenges in reducing parasitic capacitance without compromising transistor driving capability, as existing methods either increase parasitic capacitance or require thick gate insulating layers that degrade transistor performance.
Innovation Solution
An insulating layer other than the gate insulating layer is introduced between the gate electrode and source/drain electrodes, formed using a multi-tone mask to selectively etch and create overlapping wiring structures with varying thickness and width, reducing parasitic capacitance while maintaining transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a thick gate insulating layer is formed to reduce parasitic capacitance, then parasitic capacitance is reduced, but transistor driving capability is decreased
Solution Approach 1:
The insulating structure is segmented into multiple layers: a gate insulating layer and an additional insulating layer. The gate insulating layer maintains transistor performance, while the additional insulating layer specifically targets parasitic capacitance reduction at wiring intersections, separating the functions of electrical isolation and capacitance control.
Solution Approach 2:
The additional insulating layer is selectively formed only at wiring intersection portions where parasitic capacitance occurs, rather than uniformly across the entire device. This local application reduces capacitance where needed without affecting transistor characteristics in non-intersection areas.
2Object-generated harmful factors
If the gate insulating layer is formed thick to reduce parasitic capacitance, then capacitance value is reduced, but manufacturing complexity increases
Solution Approach 1:
The formation of the additional insulating layer is merged with existing manufacturing steps. The additional insulating layer is formed using the same sputtering process as the gate insulating layer, and patterning is integrated with existing photolithography steps, combining multiple functions into unified process sequences.
Solution Approach 2:
The additional insulating layer serves multiple functions: it reduces parasitic capacitance at wiring intersections, provides electrical isolation between overlapping wirings, and maintains compatibility with standard semiconductor manufacturing processes, making it universally applicable to various device configurations.
Data Source
AI summary
An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.