Semiconductor Package Wiring Pattern Solder Bump Shape Control
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Solution Overview
Problem
The semiconductor package manufacturing process is hindered by the repetitive and costly passivation and wiring pattern connection processes, which increase production time and cost.
Innovation Solution
A semiconductor package design that partially omits these processes by using a wiring pattern with isolated and inducting portions to maintain the spherical shape of solder bumps without additional passivation, and incorporates an oxide layer or organic solderability preservative to enhance corrosion resistance and reduce manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated passivation and wiring pattern connection processes are performed, then electrical connection reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the passivation layer and wiring pattern connection functions into a single integrated structure. The wiring pattern is formed directly on the chip surface with exposed pad regions that serve both as electrical connection points and as the final connection interface, eliminating the need for separate opening and connection processes that are traditionally performed after multiple passivation layers are deposited.
Solution Approach 2:
The patent extracts and eliminates the intermediate opening formation process and separate connection processes from the traditional manufacturing flow. By designing the wiring pattern to directly expose pad regions, the patent removes the need for drilling or etching openings through passivation layers to access underlying pads, thereby simplifying the overall manufacturing process while maintaining connection reliability.
2Reliability
If traditional passivation and connection processes are used, then electrical connection is achieved, but production time increases
Solution Approach 1:
The patent performs the wiring pattern formation and pad exposure as preliminary actions during the main chip fabrication process, rather than as subsequent separate steps. The wiring pattern is deposited and patterned together with other chip structures before final packaging, allowing the electrical connection interfaces to be prepared in advance and eliminating the need for time-consuming post-fabrication opening and connection operations.
3Reliability
If multiple passivation layers and connection processes are performed, then electrical connection is established, but manufacturing cost increases
Solution Approach 1:
The wiring pattern structure serves multiple functions simultaneously: it provides electrical interconnection between chip pads, acts as a partial passivation layer by covering non-active areas, and creates the exposed pad regions that serve as final connection interfaces. This multi-functionality eliminates the need for separate dedicated passivation and connection structures, reducing material usage and manufacturing steps.
Data Source
AI summary
A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.