Semiconductor Device Wiring Relocation for Surge Resistance
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Solution Overview
Problem
The surge resistance of semiconductor devices, particularly PIN diodes, is compromised when bonding wires are positioned above or near the diodes, leading to reduced adhesion between anode electrodes and PIN diodes, and potential damage to the silicide region due to concentrated electric currents.
Innovation Solution
The semiconductor device design includes a configuration where the wiring is bonded to the anode electrode in a location surrounded by silicide regions, ensuring that the bonding areas do not overlap with the silicide regions, thereby maintaining robust electrical contact and dispersing surge currents across a wider area of the PIN diode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bonding wire is disposed right above the PIN diode or in the vicinity of the PIN diode, then electrical connection is achieved, but concentrated electric current flows into the PIN diode causing decreased surge resistance and potential damage to the silicide region and PIN diode
Solution Approach 1:
The patent extracts the bonding wire from its conventional position directly above the PIN diode and relocates it to a position above the Schottky barrier diode. This separation removes the harmful concentrated current effect from the PIN diode while maintaining necessary electrical connections through the shared anode electrode.
Solution Approach 2:
The anode electrode serves as an intermediary structure that distributes the current from the bonding wire across both the Schottky barrier diode and PIN diode. By positioning the bonding wire above the Schottky barrier diode and utilizing the anode electrode as a current distribution path, the patent avoids direct concentrated current flow into the PIN diode.
2Reliability
If a bonding wire is disposed right above the PIN diode, then electrical connection is achieved, but adhesion between the anode electrode and the PIN diode is reduced
Solution Approach 1:
The patent extracts the bonding wire from the position that causes thermal deterioration directly above the PIN diode and relocates it to a safe position above the Schottky barrier diode. This prevents the bonding wire's resistive heating from damaging the adhesion interface between the anode electrode and PIN diode.
Solution Approach 2:
The patent employs a preventive design where the bonding wire is positioned above the Schottky barrier diode rather than the PIN diode, beforehand preventing thermal deterioration and adhesion loss. This proactive positioning avoids the harmful thermal effects before they can occur.
3Reliability
If the wiring is bonded to the anode electrode in a location surrounded by silicide regions, then robust electrical contact is maintained, but surge currents may be concentrated
Solution Approach 1:
The patent extracts the bonding wire from the silicide region area and positions it above the Schottky barrier diode. This maintains electrical connection quality through the anode electrode while preventing surge current concentration in the silicide region by removing the direct bonding path over it.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the surge resistance and reliability of the semiconductor device by minimizing the concentration of surge currents and maintaining strong adhesion between the anode electrode and the PIN diode, preventing thermal deterioration and maintaining rectifying characteristics.
Implementation Method 1
there has been known a Junction Barrier Schottky (JBS) diode using a Schottky barrier junction combined with a pn junction
Implementation Method 2
A silicide region may be formed between an anode electrode and the PIN diode. In this case, properties of an electric contact between the anode electrode and the PIN diode are enhanced.
Data Source
AI summary
A semiconductor device includes a first electrode, a second electrode, a first semiconductor region that is formed between the first electrode and the second electrode and is in contact with the first electrode, a second semiconductor region that is formed between the first semiconductor region and the second electrode, a contact region that is formed between the second semiconductor region and the second electrode and is in contact with the second semiconductor region and the second electrode, a plurality of third semiconductor regions that are formed between the second electrode and the first semiconductor region and are in contact with the second electrode, and a wiring that is in contact with the second electrode, a portion of the wiring bonded to the second electrode being positioned above the third semiconductor region and not positioned above the contact region.


