Semiconductor Wiring Resistivity Reversal via Dual-Layer Metal Segmentation
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Solution Overview
Problem
As semiconductor devices downscale, copper wirings become difficult to process due to increased resistivity, and tungsten wirings, while more embeddable, have higher resistivity in peripheral areas with wider widths, leading to uneven wiring resistance across different areas in memory and peripheral circuits.
Innovation Solution
A semiconductor device with a two-layer wiring structure using tungsten or molybdenum for fine, etchable first wiring parts and copper, silver, platinum, or gold for second wiring parts, selectively formed by electroless plating, reversing resistivity based on wiring width to optimize resistance across varying widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper wirings are used in semiconductor devices, then electrical conductivity is improved, but processing difficulty increases due to increased resistivity in downscaled devices
Solution Approach 1:
The patent segments the wiring structure into two distinct layers: a first wiring layer made of tungsten or molybdenum for fine-pitch interconnects where etching precision is critical, and a second wiring layer made of copper or copper alloys for broader interconnects where conductivity is paramount. This segmentation allows each layer to be optimized for its specific function, resolving the contradiction between copper's superior conductivity and its processing difficulties in downscaled devices.
Solution Approach 2:
The patent employs a composite wiring structure combining two different metal materials (tungsten/molybdenum and copper/copper alloys) in a multi-layer configuration. This composite approach leverages the etching advantages of tungsten/molybdenum for fine wirings while utilizing copper's superior conductivity in wider wirings, thereby resolving the technical contradiction between processing ease and electrical performance.
2Ease of manufacture
If tungsten wirings are used as substitute for copper, then embeddability is improved, but resistivity increases in peripheral areas with wider widths
Solution Approach 1:
The patent applies local quality by assigning different materials to different wiring layers based on their specific requirements. The first wiring layer (tungsten/molybdenum) is optimized for fine-pitch applications where etching precision is the dominant requirement, while the second wiring layer (copper/copper alloys) is optimized for broader interconnects where low resistivity is the dominant requirement. This localized material assignment resolves the contradiction between embeddability and resistivity.
3Reliability
If height of copper wirings is increased to compensate for resistivity increase, then electrical conductivity is improved, but aspect ratio increases making embedment more difficult
Solution Approach 1:
Instead of increasing the height (vertical dimension) of copper wirings to reduce resistivity, the patent transitions to a multi-layer horizontal structure. By distributing wiring functions across multiple layers with copper in the second layer, the patent achieves low resistivity through increased lateral connectivity rather than vertical thickness, thereby avoiding the aspect ratio problem while maintaining electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced resistances in both memory and peripheral circuit areas, enabling fine wiring formation and downscaling while maintaining low resistances, regardless of wiring width, by leveraging the processing advantages of tungsten and copper materials.
Implementation Method 1
selectively formed by electroless plating
Data Source
AI summary
A semiconductor device according to the present embodiment includes a first wiring part located above a substrate and made of a first metal material. A second wiring part is provided as being superimposed on the first wiring part and having a width substantially equal to that of the first wiring part. A first resistivity of the first wiring part is lower than a second resistivity of the second wiring part when the first and second wiring parts have a first width. The second resistivity is lower than the first resistivity when the first and second wiring parts have a second width larger than the first width. The semiconductor device includes both of an area in which the first and second wiring parts have the first width and an area in which the first and second wiring parts have the second width.