Semiconductor Wiring Segmentation for Warpage Control
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Solution Overview
Problem
The warpage of semiconductor chips due to distortion of the redistribution layer (RDL) becomes significant as the wafer thickness is reduced through back grinding, leading to mechanical stress and undesirable chip warping, which hinders the achievement of reduced chip size and increased memory access speed.
Innovation Solution
The warpage is reduced by dividing the thick uppermost wiring layers of the RDL into multiple thinner layers with intervening cut portions, which alleviates stress and distorts the chip less, allowing for reduced chip thickness while maintaining effective power supply distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the wafer thickness is reduced through back grinding to achieve reduced chip size, then the chip thickness is reduced, but the warpage of the chip increases due to distortion of the RDL
Solution Approach 1:
The thick uppermost wiring layer (RDL) is divided into multiple thinner wiring layers by introducing cut portions that extend through the insulating film. This segmentation reduces the stress concentration in any single layer, thereby minimizing chip warpage while maintaining the overall reduced thickness achieved through back grinding
Solution Approach 2:
Cut portions are strategically introduced at specific locations where stress accumulation is most problematic. These local modifications create stress relief zones that prevent excessive warpage in critical areas while preserving the thin profile of the chip
2Reliability
If the RDL is made thick to provide low impedance and high conductivity for power supply, then the power supply efficiency is improved, but the stress on the wafer increases causing greater warpage
Solution Approach 1:
The thick RDL is segmented into multiple thinner wiring layers separated by cut portions. Each layer maintains sufficient conductivity for power supply while the segmentation reduces the cumulative stress on the wafer, preventing excessive warpage that would occur with a single thick layer
Solution Approach 2:
The power supply function is distributed across multiple layers in the vertical dimension rather than concentrated in a single thick layer. This multi-layer approach maintains the low impedance and high conductivity requirements while reducing stress through the vertical distribution of conductive material
3Reliability
If the wiring layers of RDL are made elongated to connect pads arranged along opposite sides, then the power supply distribution is improved, but the stress pulls the pads toward each other causing warpage
Solution Approach 1:
The elongated wiring layers are divided into multiple segments by introducing cut portions at strategic intervals. This segmentation maintains the power supply distribution function across the chip while reducing the continuous stress that would otherwise pull pads toward each other and cause warpage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes chip warpage and stress, enabling the reduction of chip thickness while maintaining the integrity of power supply distribution, thus addressing the challenge of achieving smaller chip sizes with high memory access speed and low power consumption.
Implementation Method 1
Because there is a difference in coefficient of thermal expansion (CTE) between the wafer and the thin film, the difference in CTE causes the wafer to be distorted in a manner to bend towards the thin film
Data Source
AI summary
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes a first group of wiring layers of an internal redistributing layer (iRDL) providing a power supply voltage and a second group of wiring layers of another iRDL providing a ground voltage. The first group of wiring layers providing the power supply voltage from a first side of the semiconductor device to a second side of the semiconductor device opposite to the first side are at least partially separated by at least one cut portion between the first side and the second side.