Semiconductor Wiring Structures via Segmented Etching
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Solution Overview
Problem
The challenge in manufacturing highly integrated semiconductor devices, such as DRAM, lies in forming wiring structures with extremely small dimensions, particularly in creating precise contact plugs and conductive lines, which existing methods struggle to achieve effectively.
Innovation Solution
A method involving the formation of an isolation pattern on a substrate with active patterns, buried gate structures, and insulation layers to create openings for wiring structures, where the insulation pattern is etched to expose contact regions, and a conductive layer is formed to fill and shape these openings, ensuring precise dimensions and electrical insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional etching methods are used to form contact plugs, then the manufacturing process is simple, but the wiring structure dimensions cannot be reduced to extremely small sizes
Solution Approach 1:
The patent segments the formation process into multiple stages: first forming a preliminary opening through the first insulation layer, then forming a second opening through the isolation pattern, and finally forming the wiring structure. This multi-stage segmentation allows each step to be optimized independently, enabling precise control of extremely small dimensions while maintaining process feasibility
Solution Approach 2:
The patent performs preliminary actions by forming the first insulation layer and creating the preliminary opening before forming the final wiring structure. The insulation pattern is formed in advance on the sidewall of the preliminary opening to define the second opening. These preliminary structures guide subsequent processing steps to achieve the required precision for extremely small wiring dimensions
2Productivity
If the wiring structure width is reduced to increase integration, then device integration increases, but electrical insulation between adjacent structures becomes difficult to maintain
Solution Approach 1:
The patent introduces an insulation pattern as an intermediary structure formed on the sidewall of the preliminary opening. This insulation pattern extends into the second opening and provides electrical isolation between adjacent wiring structures. The intermediary insulation layer enables closer spacing of conductors (increasing integration) while maintaining reliable electrical insulation through the inserted dielectric material
Solution Approach 2:
The patent moves the insulation function from a horizontal separation (between adjacent wiring structures at the same level) to a vertical dimension by forming the insulation pattern on the sidewall that extends downward into the second opening. This dimensional transition allows insulation to be achieved through the depth of the structure rather than relying solely on horizontal spacing, enabling higher integration while maintaining insulation reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of semiconductor devices with accurately sized and insulated wiring structures, enhancing device integration and performance by allowing for smaller feature sizes and effective electrical isolation.
Implementation Method 1
A portion of the first insulation layer on the first contact region and an upper portion of the first contact region thereunder are etched to form a preliminary opening exposing at least the first contact region. The isolation pattern exposed by a sidewall of the preliminary opening is etched to form an opening
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.