Semiconductor Wiring Migration Resistance via Selective Silicide
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Solution Overview
Problem
Existing methods for forming copper silicide on copper wirings in semiconductor devices result in increased wiring resistance and do not effectively prevent electromigration and stress migration, particularly at the connection points between wirings and vias.
Innovation Solution
A semiconductor device and manufacturing method where a different electrically conductive film, containing a metal different from the main component of the wiring, is selectively formed on the top of the wiring where it connects to the via, using the insulating film as a mask, without the need for additional photoresist processes, to enhance resistance against migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper silicide is formed on the entire upper surface of the copper wiring, then resistance against migration of the copper wiring is improved, but wiring resistance becomes higher
Solution Approach 1:
The patent applies local quality by forming copper silicide selectively only at the bottom of via-holes where copper wiring is connected, rather than on the entire upper surface of the copper wiring. This localized treatment provides migration resistance precisely where the via-hole connection creates stress, while preserving the low-resistance properties of the bulk copper wiring surface.
2Object-affected harmful factors
If copper wirings are used to decrease electrical resistance, then electrical resistance is reduced, but electromigration or stress migration of copper wirings at the bottom of via-holes becomes a problem
Solution Approach 1:
The patent addresses this contradiction by applying copper silicide locally at the via-hole bottom where stress migration occurs, rather than uniformly across the entire copper wiring. This localized protection maintains the low electrical resistance of the copper wiring while providing targeted migration resistance at the critical connection point.
Solution Approach 2:
The patent uses composite materials by combining copper (for low electrical resistance) with silicon to form copper silicide (for migration resistance). This composite structure allows the wiring to benefit from both materials: copper provides excellent conductivity while the copper silicide layer at the via-hole bottom provides protection against electromigration and stress migration.
3Manufacturing precision
If a photoresist process is added to selectively form the different element containing electrically conductive film, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by using the insulating film itself as the mask for selective copper silicide formation. The insulating film that already exists in the structure serves the dual purpose of electrical insulation and pattern definition, eliminating the need for additional photoresist coating and etching steps while maintaining precise selective formation of the copper silicide layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively raises the resistance against migration, suppresses the increase in wiring resistance, and improves the yield of semiconductor devices by selectively forming a copper silicide layer or alloy at the connection points between the wiring and via, thereby reducing stress migration.
Implementation Method 1
If Si is used as a different element, the surface of the wiring metal film may be silicided to form a silicide layer to raise the resistance of the wiring against the migration
Data Source
AI summary
A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on the first interconnect (wiring) 112 so that the via is connected to the first interconnect (wiring) 112, and a different element containing electrically conductive film 114. The different element containing electrically conductive film is formed selectively on a site on the top of the first interconnect (wiring) 112 where the first wiring is contacted with the bottom of the via 128. The different element containing electrically conductive film contains a metal of a main component of the first interconnect (wiring) 112 and a different element different from the metal of the main component.