Semiconductor Wiring Spacer Insulation for Integration Density
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining desired insulating performance between electrical components in both high and low integration density regions, particularly with the reduction in design rules, where achieving effective insulation between adjacent connection wiring layers in the peripheral circuit region becomes difficult due to reduced spacing.
Innovation Solution
A semiconductor device structure is developed with a spacer insulating film formed on the inner and outer sidewall surfaces of connection wiring layers in both memory cell and peripheral circuit regions, using silicon nitride films as spacers within holes extending through interlayer insulating films, ensuring electrical insulation and preventing structural contact between adjacent wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between electrical components is reduced to increase integration density, then productivity and integration degree are improved, but insulating performance and reliability deteriorate
Solution Approach 1:
The invention transitions from two-dimensional planar insulation to three-dimensional insulation by forming spacer insulating films on the side surfaces of connection wiring layers. This vertical/dimensional approach allows insulation to extend beyond the horizontal plane, enabling effective electrical isolation even when horizontal spacing between components is reduced, thus resolving the contradiction between integration density and insulating performance
Solution Approach 2:
The spacer insulating film acts as an intermediary element between adjacent connection wiring layers. This intermediate insulating structure prevents direct electrical contact and reduces parasitic capacitance, maintaining reliability while allowing closer component spacing for higher integration density
2Ease of manufacture
If a uniform insulating structure is applied to both memory cell and peripheral circuit regions, then manufacturing simplicity is maintained, but insulating performance cannot be optimized for different integration densities
Solution Approach 1:
The invention applies different insulating structures to different regions: in the memory cell region with high integration density, spacer insulating films are formed on connection wiring layers to provide additional side-surface insulation, while in the peripheral circuit region with lower integration density, conventional planar insulating films suffice. This localized differentiation optimizes insulating performance for each region's specific integration requirements while maintaining overall manufacturing feasibility
Data Source
AI summary
A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provided in each region so as to interpose an interlayer insulating film, a plurality of connection wiring layers formed in a plurality of holes which are formed in the interlayer insulating film so as to extend through the conductive layers of each region, the connection wiring layers electrically connecting the conductive layers, and a spacer insulating film functioning as a spacer which is formed on inner sidewall surfaces of the holes and outer sidewall surfaces of the connection wiring layers in each region.