Semiconductor Device Wiring Substrate DC Cut-off Capacitor Integration
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Solution Overview
Problem
The miniaturization of electronic devices is hindered by the complex wiring layout required for high-speed signal transmission paths, which includes DC cut-off capacitors, leading to electrical characteristics and reliability issues due to the need for numerous interlayer conductive paths.
Innovation Solution
Incorporating a DC cut-off capacitor within the semiconductor device on a wiring substrate, rather than on the motherboard, simplifies the wiring layout and reduces the number of interlayer conductive paths, enhancing electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a DC cut-off capacitor is mounted on the motherboard outside the semiconductor device, then the wiring layout becomes complex with numerous interlayer conductive paths, but the capacitor can be easily replaced or modified
Solution Approach 1:
The patent combines the DC cut-off capacitor with the semiconductor device by mounting it on the same wiring substrate (motherboard) in close proximity to the semiconductor chip. This merging eliminates the need for complex interlayer conductive paths between separate devices, simplifying the wiring layout while maintaining the capacitor's functional integration in the signal transmission path.
2Device complexity
If the capacitor is placed close to the semiconductor chip to simplify wiring, then the number of interlayer conductive paths is reduced, but electrical characteristics and reliability may deteriorate due to layout issues
Solution Approach 1:
The patent applies local quality by positioning the capacitor at a specific location on the wiring substrate - close to the semiconductor chip but with optimized spacing and orientation. This localized placement reduces the number of interlayer conductive paths while maintaining electrical characteristics through careful control of the capacitor's position relative to the chip electrodes and signal paths.
3Volume of moving object
If the capacitor is integrated inside the semiconductor device package, then miniaturization is achieved, but the wiring layout becomes more complex and reliability may be compromised
Solution Approach 1:
The patent utilizes the two-dimensional plane of the wiring substrate by placing the capacitor in the same plane as the semiconductor chip rather than stacking it vertically inside the device package. This dimensional approach achieves miniaturization by efficient planar layout while avoiding the complex three-dimensional wiring and reliability issues that would arise from internal integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the miniaturization of electronic devices by simplifying the wiring layout and reducing impedance discontinuities in high-speed transmission paths, thereby enhancing the electrical characteristics and reliability of semiconductor devices.
Implementation Method 1
This capacitor is intended to cut off a DC component contained in an AC signal and thus called a direct current (DC) cut-off capacitor or an alternate current (AC) coupling capacitor
Data Source
AI summary
A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.