Semiconductor Wiring via Substrate Etching and Grinding
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Solution Overview
Problem
Current semiconductor device wiring technologies face limitations in forming thick metal wiring with high aspect ratios and high-quality inductors due to thickness and line width constraints, leading to degraded performance and increased module thickness.
Innovation Solution
A method involving selective etching of a silicon substrate, coating with a metal layer, filling with organic material, forming via holes, and grinding the substrate to connect metal wiring through these holes, while ensuring the metal layer's thickness is optimized for high-frequency signals and line width expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photoresist and electroplating are used to form metal wiring, then the wiring can be formed with conventional processes, but the maximum thickness and aspect ratio of the wiring are limited
Solution Approach 1:
The patent transitions from planar metal wiring formation to three-dimensional wiring structures by etching deep holes in the substrate and forming metal patterns on the etched surfaces. This dimensional change allows achieving high aspect ratios and greater effective thickness without being constrained by photoresist thickness limitations, as the metal is deposited on vertically extended surfaces rather than horizontal planes.
Solution Approach 2:
The patent introduces an organic material as an intermediary substance to fill the etched portions of the substrate. This organic material serves as a foundation and support structure upon which the metal layer is formed, enabling the creation of thick, high aspect ratio wiring structures that would be impossible to achieve with conventional photoresist-based electroplating alone.
2Reliability
If metal layer thickness is increased to widen line width, then electrical performance improves, but high frequency signal loss increases due to skin effect
Solution Approach 1:
The patent applies different metal layer thicknesses to different regions of the wiring structure. The metal layer is formed to have optimal thickness for high frequency signals in areas where skin effect is critical, while maintaining sufficient conductivity. The coating is performed based on skin depth considerations, ensuring neighboring metal parts do not contact, thus locally optimizing both electrical performance and high frequency characteristics.
Solution Approach 2:
The patent creates a composite structure consisting of the organic material substrate and the metal layer coating. This composite approach allows the organic material to provide structural support and electrical insulation, while the metal layer provides conductivity. The combination enables achieving good electrical performance without requiring excessively thick metal layers that would cause high frequency losses.
3Ease of manufacture
If conventional thin film inductor structures are used, then manufacturing is simplified, but line width is limited leading to degraded inductor quality
Solution Approach 1:
The patent moves from thin planar inductor structures to three-dimensional inductor configurations by utilizing deep etched holes in the substrate. The metal pattern is formed on the vertical sidewalls and bottom of these etched structures, creating inductors with effectively larger line widths and better quality factors while maintaining compatibility with existing manufacturing processes like spin coating and standard etching techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor device wirings with significantly wider line widths and reduced resistance, enhancing electrical performance and shielding capabilities, suitable for high-power semiconductor devices with three-dimensional structures.
Implementation Method 1
the coating may be performed based on a skin depth of a high frequency signal in a way that neighboring parts of the metal layers are not in contact with each other
Implementation Method 2
forming organic material in the first surface to fill an etched portion and cover the coated metal layer
Implementation Method 3
forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes
Implementation Method 4
grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion
Data Source
AI summary
A method for forming a wiring for a semiconductor device according to an aspect of the present invention includes: forming a predetermined pattern on a first surface of a silicon substrate by selectively etching the first surface; coating, with a metal layer, a selected area of the first surface, including an area whereat the predetermined pattern is formed; forming organic material in the first surface to fill an etched portion and cover the coated metal layer; forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes; and grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion.