Semiconductor Device Wiring Substrate Terminal Pitch Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of terminals on semiconductor chips leads to a larger outline size due to the need for wider land-to-land pitch in flip chip bonding, which increases the size of semiconductor devices.
Innovation Solution
The semiconductor device features a wiring substrate with first and second type terminals arranged in a specific pattern, where the row-to-row pitch is varied to minimize the number of lead-out lines between terminals, allowing for a more compact layout by optimizing the distribution of lead-out lines and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of terminals on semiconductor chip increases, then the function of semiconductor device is improved, but the outline size of semiconductor device becomes larger
Solution Approach 1:
The patent applies local quality by differentiating between two types of terminals: first terminals (peripheral) with equal row-to-row pitch, and second terminals (inner) with larger row-to-row pitch. This localized differentiation allows the inner terminals to have sufficient spacing for lead-out lines while maintaining high density at the periphery, thus increasing total terminal count without proportionally increasing the overall device area.
Solution Approach 2:
The patent utilizes the third dimension (vertical layering) by forming lead-out lines in multiple wiring layers beneath the terminal surface. This allows lead-out lines to route under terminals vertically rather than only horizontally, reducing the horizontal space needed for lead-out connections and enabling higher terminal density within the same planar area.
2Quantity of substance
If bump electrodes are arranged in area array fashion over the whole main surface, then the number of terminals becomes sufficient, but the land-to-land pitch must be widened
Solution Approach 1:
The patent implements local quality by applying different pitch requirements to different terminal regions: peripheral terminals maintain equal, smaller pitch for high density, while inner terminals have larger pitch to accommodate lead-out lines. This localized pitch differentiation allows area array arrangement to achieve sufficient terminal count without requiring uniform widening of land-to-land pitch across the entire array.
Solution Approach 2:
The patent segments the terminal array into two distinct groups: first terminals at the periphery and second terminals in the inner region. This segmentation allows each group to have optimized spacing characteristics - the peripheral terminals can be densely packed while the inner terminals have adequate spacing for lead-out line routing, thus achieving high overall terminal count without uniform pitch increase.
3Reliability
If lead-out lines are drawn out from all lands toward the outside of area-arrayed region, then electrical connectivity is maintained, but the number of lead-out lines passing between lands becomes maximum
Solution Approach 1:
The patent segments terminals into first terminals (peripheral) and second terminals (inner), where only the inner terminals require lead-out lines to be drawn out. This segmentation reduces the total number of lead-out lines that must pass between terminals, as peripheral terminals can directly connect to external connections without requiring long lead-out paths through the terminal array.
Solution Approach 2:
The patent utilizes vertical wiring layers to route lead-out lines beneath terminals rather than only through the horizontal plane between terminals. This three-dimensional routing approach reduces the number of lead-out lines that must pass between visible terminal rows, simplifying the overall interconnection structure while maintaining electrical connectivity.
Data Source
AI summary
A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time.