Semiconductor Wiring Structure with Variable Line Widths via Spacer Patterning
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Solution Overview
Problem
The increasing integration of integrated circuit devices leads to challenges in forming fine patterns in semiconductor devices due to the limitations of conventional photolithography processes, resulting in non-uniform wiring structures and increased device failures.
Innovation Solution
A method using a single photolithography process and a single mask pattern to form a wiring structure for semiconductor devices by creating spacers on a substrate with different preliminary mask structures, allowing for the formation of conductive patterns with varying line widths in different regions through a spacer patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography process is used to form wiring structures, then the process is simple and straightforward, but the resolution limit prevents formation of fine patterns with critical dimension less than 40 nm
Solution Approach 1:
The patent applies segmentation by dividing the single photolithography exposure step into multiple sequential exposure steps. First, a preliminary mask pattern is formed and exposed. Then, a second mask pattern with different pitch is exposed on the same substrate. This segmentation allows the formation of fine patterns (first pattern) and larger patterns (second pattern) in the same cell area using conventional photolithography equipment, overcoming the resolution limit while managing process complexity through systematic multi-step exposure.
2Manufacturing precision
If double patterning technology or spacer patterning technology is used to form fine patterns, then the critical dimension limit is overcome, but the process complexity increases significantly
Solution Approach 1:
The patent merges the formation of first pattern (fine pattern) and second pattern (larger pattern) into a single integrated process flow within the same cell area. Both patterns are formed using the same photolithography equipment and similar processing steps, but with different mask patterns and exposure conditions. This merging approach achieves fine pattern formation without requiring completely separate patterning processes, thereby reducing overall process complexity while maintaining manufacturing precision.
3Adaptability or versatility
If different mask patterns with different pitches are used in the same cell area, then patterns with varying line widths can be formed, but the process alignment and control become more difficult
Solution Approach 1:
The patent applies local quality by using different mask patterns specifically tailored for different regions within the same cell area. The first mask pattern is designed with pitch suitable for forming fine patterns (first pattern), while the second mask pattern has larger pitch for forming larger patterns (second pattern). Each mask pattern is optimized for its specific purpose, allowing versatile line width variation while maintaining alignment precision through region-specific pattern design and controlled exposure parameters.
Data Source
AI summary
A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region. An insulation layer is patterned using the first and second mask patterns as respective masks to define a first trench in the first region and a second trench in the second region having a greater width than the first trench, and first and second conductive patterns are formed in the first and second trenches.