Semiconductor Device Multi-Level Wiring Via Structure

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Solution Overview

Problem

As semiconductor elements continue to downscale, there is a challenge in stably forming wirings and via holes for connecting them across multiple metal levels, which affects the routability and reliability of semiconductor devices.

Innovation Solution

The semiconductor device incorporates a via structure that directly connects wirings across different metal levels, using interlayer insulating layers and filling layers to enhance connectivity and reduce unnecessary space, thereby improving routability and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional wiring connection methods are used across multiple metal levels, then the wiring structure is simpler, but the routability is poor and additional space is required at specific metal levels

Engineering Contradiction:
ImproveroutabilityVSAvoidwiring structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces via holes that extend in the vertical dimension to directly connect wirings across multiple metal levels (first metal level to second metal level), eliminating the need for intermediate connections at the second metal level. This dimensional approach to connectivity dramatically improves routability by allowing direct through-substrate connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The via holes are formed within and penetrate through the interlayer insulating layers, nesting the conductive pathways within the insulating structure. The via holes are embedded in the interlayer insulating layer, creating a nested configuration that achieves long-distance connectivity without adding external complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Adaptability or versatility

If via holes are used to connect wirings across multiple metal levels, then the routability is improved, but the manufacturing difficulty increases

Engineering Contradiction:
ImproveroutabilityVSAvoidvia hole formation difficulty
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The interlayer insulating layer is formed preliminarily before via hole formation, providing a pre-prepared medium in which via holes can be easily formed. This preliminary formation of the insulating layer with appropriate properties facilitates subsequent via hole creation and reduces manufacturing difficulty.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interlayer insulating layer serves as an intermediary material that enables via hole formation and wiring connection. This intermediary layer with controlled dielectric properties and etch selectivity makes the via hole formation process more manageable and reduces overall manufacturing difficulty.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If direct via connections are implemented across metal levels, then the IR drop is reduced and reliability is improved, but the process complexity increases

Engineering Contradiction:
Improveelement reliabilityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interlayer insulating layer performs multiple functions: it provides electrical insulation between metal levels, serves as a medium for via hole formation, and enables direct wiring connections. This multi-functionality reduces the need for additional specialized layers or processes, thereby limiting the increase in fabrication process complexity while achieving improved reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If additional space is allocated at specific metal levels for connectivity, then the wiring connections are more stable, but the integration density decreases

Engineering Contradiction:
Improvewiring connection stabilityVSAvoidintegration density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By transitioning connectivity from a two-dimensional planar approach to a three-dimensional vertical approach via via holes, the patent eliminates the need for additional lateral space at intermediate metal levels. This dimensional shift maintains wiring connection stability while preserving integration density by utilizing the vertical dimension for connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11075160B2Semiconductor device and method for fabricating thereof
Publication Date: 2021.07.27 SAMSUNG ELECTRONICS CO LTD
  • US11075160B2 patent drawing
  • US11075160B2 patent drawing
  • US11075160B2 patent drawing

AI summary

A semiconductor device is provided. The semiconductor device includes a first wiring and a second wiring disposed at a first metal level, a third wiring and a fourth wiring disposed at a second metal level different from the first metal level, a first via which directly connects the first wiring and the third wiring, a fifth wiring disposed at a third metal level between the first metal level and the second metal level and connected to the second wiring, and a second via which directly connects the fourth wiring and the fifth wiring.