Semiconductor Work Function Layer Etching Control
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Solution Overview
Problem
The existing methods for manufacturing transistors face challenges in scaling down feature sizes and achieving optimal performance due to incomplete removal of work function layers, leading to issues with etching rates and device performance.
Innovation Solution
A semiconductor structure and method involving a combined etching process with oxide etching and main etching processes, along with hydrophilic treatments and DI water rinsing, to accurately remove initial work function layers and form work function layers with varying thicknesses on a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single etching process is used to remove the initial work function layer, then the manufacturing process is simple, but the etching is incomplete and device performance is poor
Solution Approach 1:
The patent divides the etching process into two distinct segments: an oxide etching process using HF solution to remove oxide layers, followed by a main etching process using H2O2-based solution to remove the initial work function layer. This segmentation allows each process to be optimized for its specific function, ensuring complete removal while maintaining controllable complexity
Solution Approach 2:
The oxide etching process acts as an intermediary step between the initial work function layer formation and the main etching process. By first removing the oxide layer, it prepares the surface for the subsequent main etching process, enabling complete and clean removal of the work function layer without direct confrontation between conflicting requirements
2Manufacturing precision
If the work function layer is not completely removed, then the manufacturing process is simpler, but the transistor performance cannot be optimized
Solution Approach 1:
The oxide etching process is performed as a preliminary action before the main etching process. By first removing the oxide layer that forms on the work function layer, it prevents interference with the subsequent main etching process, ensuring precise and complete removal of the work function layer
Solution Approach 2:
The patent changes the chemical parameters between the two etching processes by using different solutions (HF for oxide etching, H2O2-based for main etching) and controlling temperatures (50-80°C for main etching). These parameter changes enable precise control over the etching depth and rate, achieving complete removal while maintaining manufacturing efficiency
3Adaptability or versatility
If different transistors are formed on the same substrate, then the functionality is enhanced, but the work function adjustment becomes more complex
Solution Approach 1:
The patent applies local quality by forming different thicknesses of the work function layer in different regions of the substrate. The combined etching process enables selective removal of the initial work function layer to achieve region-specific thickness control, allowing different transistor functions (such as NFET and PFET) to be formed on the same substrate with appropriate work function adjustments
Solution Approach 2:
The combined etching process is performed in periodic cycles, alternating between oxide etching and main etching steps. This periodic action allows for controlled, incremental removal of the work function layer, enabling precise thickness adjustment in different regions to achieve the desired work function values for various transistor types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures complete removal of work function layers, improving transistor performance by enhancing etching efficiency and preventing incomplete etching, which allows for the formation of transistors with different functions on the same substrate.
Implementation Method 1
performing an oxide etching process to etch the plurality of initial work function layers
Implementation Method 2
performing a main etching process on the plurality of initial work function layers to remove an exposed initial work function layer
Implementation Method 3
performing a first surface treatment process on the plurality of initial work function layers formed in the first gate opening
Data Source
AI summary
A method for forming a semiconductor structure includes forming a dielectric layer on a substrate, including a first region and a second region; forming a first gate opening and a second gate opening in dielectric layer of the first region and the second region, respectively; forming initial work function layers on bottom and sidewall surfaces of the first gate opening and the second gate opening; and performing at least one cycle of a combined etching process to etch the initial work function layers formed in the first gate opening and form a work function layer in the second gate opening from the initial work function layers. Each cycle of the combined etching process includes performing an oxide etching process to etch the initial work function layers; and then performing a main etching process on the initial work function layers to remove an exposed initial work function layer.