Semiconductor Write Buffer Segmentation for PCRAM Speed
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Solution Overview
Problem
Conventional memory devices, such as PCRAM, face performance bottlenecks due to the significant time difference between set and reset operations, which slows down write operations as they are often performed simultaneously across memory cells.
Innovation Solution
A semiconductor apparatus comprising a controller, a buffer, and a memory device that processes write requests by storing data in a first buffer, performing logic operations with data from the second buffer, and updating the memory device, thereby optimizing write operations by separating and prioritizing set and reset operations based on available buffer space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If set and reset operations are performed simultaneously on memory cells during write operations, then data can be written to multiple cells in parallel, but the write operation time is dictated by the slower set operations, reducing overall write performance
Solution Approach 1:
The patent segments the write operation into two independent phases: a first phase that performs only reset operations (faster operation) and a second phase that performs only set operations (slower operation). By separating these operations in time, the system can complete reset operations quickly without being blocked by slower set operations, thereby improving overall write performance while still allowing parallel processing of multiple memory cells.
2Reliability
If set operations are performed on all memory cells during write operations, then all cells can be updated uniformly, but the operation time is determined by the longest set operation time, creating a performance bottleneck
Solution Approach 1:
The patent divides the write operation into sequential phases where reset operations are completed first, followed by set operations. This segmentation ensures that all memory cells are updated completely (maintaining reliability) while the faster reset operations complete quickly, and the slower set operations execute in a dedicated phase without blocking other operations, thereby improving throughput.
Solution Approach 2:
The patent performs reset operations as a preliminary action before performing set operations. Since reset operations are faster and can be completed more quickly, executing them first allows the system to reach a stable state faster, and then the slower set operations can execute without delaying the overall process. This preliminary execution of faster operations improves overall productivity while ensuring complete data updates.
Data Source
AI summary
A semiconductor apparatus may include: a buffer configured to store write request data input in response to a write request from a host; a memory device configured to store data evicted from the buffer; and a controller configured to control the buffer and the memory device to process the write request.