Semiconductor Device Write Recovery Time Control
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Solution Overview
Problem
Conventional semiconductor devices fail to secure write recovery time due to misidentification of pre-charge commands caused by noise from Process, Voltage, and Temperature (PVT) variations, leading to corrupted data storage.
Innovation Solution
A semiconductor device with internal circuits that generate pulses and a transfer control unit to prevent non-write commands from being transferred during specific activation periods, ensuring write recovery time is maintained by generating a first pulse for a write command and a second pulse for a delayed write command, with a command mask signal to block misidentified pre-charge commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor device adjusts input time of pre-charge command to secure write recovery time, then write recovery time is maintained, but the device cannot detect misidentified pre-charge commands caused by noise, leading to data corruption
Solution Approach 1:
The patent applies preliminary action by generating a mask signal in advance that covers the write recovery period. This mask signal is prepared before the potential misidentified pre-charge command arrives, allowing the system to proactively prevent command misidentification rather than reacting after detection. The mask signal is generated immediately upon receiving a write command and remains active for the required recovery period, blocking any erroneous commands that might be misidentified during this critical window.
Solution Approach 2:
The patent introduces a mask signal as an intermediary element between the command input and the internal circuit. This mask signal acts as a mediator that selectively blocks commands during the write recovery period. When a write command is received, the mask signal is generated and prevents any subsequent commands (including misidentified pre-charge commands) from reaching the internal circuit until the recovery period elapses, thus protecting data integrity without requiring complex detection mechanisms.
2Productivity
If the semiconductor device operates at high speed, then productivity increases, but noise from PVT variations causes pre-charge commands to be misidentified, compromising data stability
Solution Approach 1:
The patent applies preliminary anti-action by generating a mask signal that preemptively counteracts the potential harmful effect of misidentified pre-charge commands. Instead of trying to detect or correct errors after they occur, the mask signal is generated in advance upon receiving a write command and actively prevents any erroneous commands during the write recovery period. This anti-action approach maintains high-speed operation while reliably blocking noise-induced misidentifications without requiring slower detection and correction cycles.
3Device complexity
If misidentified pre-charge commands are allowed to pass through, then device complexity remains low, but write recovery time cannot be secured and data becomes corrupted
Solution Approach 1:
The patent introduces a mask signal as an intermediary element between the command input and the internal circuit. This mask signal acts as a mediator that selectively blocks commands during the write recovery period. When a write command is received, the mask signal is generated and prevents any subsequent commands (including misidentified pre-charge commands) from reaching the internal circuit until the recovery period elapses, thus protecting data integrity without requiring complex detection mechanisms.
Solution Approach 2:
The patent extracts and isolates the write recovery period as a distinct time window that requires special protection. By separating this critical period from normal command processing and applying a dedicated mask signal only during this extracted time window, the system maintains simple overall architecture while providing focused protection against data corruption during the vulnerable recovery period.
Data Source
AI summary
A semiconductor device may include an internal circuit configured to perform write operations in response to each of a plurality of write commands, wherein the plurality of write commands are sequentially input to the internal circuit, a first pulse generation unit configured to generate a first pulse activated during a first delay amount in response to a write command, a second pulse generation unit configured to generate a second pulse activated during the first delay amount in response to a delayed write command out of the plurality of write commands after a second delay amount from the activation time of the first pulse, and a transfer control unit configured to prevent commands other than the plurality of write commands from being transferred to the internal circuit during a sum of the activation period of the first pulse and the activation period of the second pulse.