Semiconductor Yield Prediction From Layout-Mapped Defect Recognition

Solution Overview

Problem

In semiconductor manufacturing, defects detected during the process often lead to scrapped chips or wafers, with electrical testing performed after production, resulting in sunk costs and time that cannot be recovered.

Innovation Solution

A yield rate prediction method and system that uses a recognition model to predict the probability of functional errors in semi-final products by establishing a correspondence between circuit paths and integrated circuit layouts, training on defective points, and predicting yield rates to determine if the manufacturing process should be suspended.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electrical testing is performed after semiconductor device manufacturing, then functional errors can be detected, but sunk cost and time cannot be recovered

Engineering Contradiction:

Improvedetection of functional errorsVSAvoidsunk time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing yield rate prediction during the manufacturing process using a recognition model that analyzes defective points on stacking layers. This allows functional errors to be predicted before the manufacturing process completes, enabling early detection without waiting for post-manufacturing electrical testing. The recognition model processes imaging data from intermediate stages to forecast final product yield, thereby recovering time and cost by identifying defects earlier in the production flow.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If electrical testing is performed after semiconductor device manufacturing, then functional errors can be detected, but sunk cost cannot be recovered

Engineering Contradiction:

Improvedetection of functional errorsVSAvoidsunk cost

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by performing yield rate prediction during the manufacturing process using a recognition model that analyzes defective points on stacking layers. This allows functional errors to be predicted before the manufacturing process completes, enabling early detection without waiting for post-manufacturing electrical testing. The recognition model processes imaging data from intermediate stages to forecast final product yield, thereby recovering time and cost by identifying defects earlier in the production flow.

Inventive Principle:

Principle #10Preliminary action

3Loss of time

If defect detection is performed during manufacturing process, then yield rate can be predicted and process suspension can be determined, but additional detection complexity is introduced

Engineering Contradiction:

Improverecovery of manufacturing timeVSAvoiddetection system complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies copying by using imaging data (such as SEM images) to create a digital representation of the semiconductor structure at intermediate manufacturing stages. The recognition model processes these image copies to identify defective points and predict yield rates without requiring physical intervention or complex additional detection hardware. This approach reduces detection system complexity while enabling early defect identification during the manufacturing process.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS20220076146A1Yield rate prediction method, yield rate prediction system and model training device of semiconductor manufacturing process

Publication Date: 2022.03.10 UNITED MICROELECTRONICS CORP

AI summary

A yield rate prediction method, a yield rate prediction system, and a model training device of a semiconductor manufacturing process are provided. The yield rate prediction method of a semiconductor manufacturing process includes the following steps. A correspondence relation between a circuit path of a netlist and an integrated circuit layout is established. Several defective points on several stacking layers are obtained. A recognition model is trained to recognize a fault occurred on the circuit path according to the defective points. A probability of the fault occurred on the circuit path of a semiconductor semi-final product according to the recognition model is recognized. A yield rate of the semiconductor semi-final product is predicted according to the probability.