Semiconductor Yield Indicators for Granular Component Failure Tracking
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Solution Overview
Problem
Traditional yield analysis methods for semiconductor devices, particularly in complex multi-chiplet and logic circuit block products, lack the granularity to identify and track individual component failures, masking the true impact of yield excursions and requiring sequential fixing of failures based on priority.
Innovation Solution
The Human Readable Yield (HRY) framework generates granular yield indicators per component using data encoding and compression techniques, allowing for individual tracking and monitoring of circuit components, with drill-down capabilities for detailed analysis and standardized data formats for efficient indicator generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional yield analysis methods are used, then overall yield percentage can be calculated, but granular component-level failure tracking is lost
Solution Approach 1:
The patent segments the yield analysis data into hierarchical levels (device level, chiplet level, component level) using a structured data format with parent-child relationships. This allows granular tracking of individual component failures while maintaining overall yield context, resolving the contradiction between measurement precision and data structure complexity.
Solution Approach 2:
The patent implements a nested data structure where child elements (component-level test results) are contained within parent elements (chiplet-level, device-level results). This nesting approach enables detailed component tracking without requiring completely separate data systems, thus improving granularity while managing complexity through structured organization.
2Measurement precision
If detailed component-level tracking is implemented, then individual failure identification improves, but computational time increases
Solution Approach 1:
The patent performs preliminary data encoding and compression during the test execution phase, transforming detailed component-level test results into a compact hierarchical format. This preliminary processing reduces the amount of data that needs to be processed later during yield analysis, thereby improving failure identification precision while reducing computational time requirements.
Solution Approach 2:
The patent changes the data representation parameters by encoding test results using standardized fields and compression techniques. This parameter transformation converts verbose raw test data into a condensed hierarchical structure that maintains detailed failure information while significantly reducing computational overhead for analysis.
3Ease of operation
If sequential failure fixing based on priority is used, then resource allocation is simplified, but true impact of yield excursions is masked
Solution Approach 1:
The patent implements feedback mechanisms that track the status of individual components and chiplets throughout the manufacturing process. By maintaining continuous feedback on component-level test results and their relationship to overall yield, the system enables informed resource allocation decisions while preserving complete information about yield excursion impacts, allowing simultaneous simplification and comprehensive tracking.
Solution Approach 2:
The patent adds a dimensional layer to failure tracking by introducing temporal and contextual dimensions to the hierarchical data structure. This allows the system to track failures not just sequentially by priority, but also by their impact on overall yield, enabling both simplified resource allocation and complete information preservation through multi-dimensional data organization.
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed to generate semiconductor product yield indicators. Examples disclosed herein are to cause at least one processor circuit to encode a data string to represent a sequence of test results corresponding to a plurality of test instances performed by automated test equipment on a first device under test. Disclosed examples are also to cause the at least one processor circuit to output the data string to a second device.