Semi-Dense Array Contact and Via Layout for IC Interconnects
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Solution Overview
Problem
Current photolithographic processes struggle to form metal interconnects, vias, and contacts at minimum pitches due to diffraction limits, making it difficult to connect networks of metal lines across different interconnect levels in integrated circuits, especially when feature sizes and spacings approach or exceed the equipment's capabilities.
Innovation Solution
The use of photolithographic printers to form metal interconnect lines, vias, and contacts at minimum pitches, with specific illuminator orientations and apertures that allow for semi-dense array configurations, enabling smaller pitch distances and improved connectivity between metal lines and components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processes are used to form metal interconnects, vias, and contacts, then patterns can be generated for horizontal metal lines, but the minimum pitch for contacts and vias is larger than for metal lines due to diffraction limits
Solution Approach 1:
The patent applies different pitch requirements to different feature types: metal interconnect lines use the smaller minimum pitch while contacts and vias use the larger minimum pitch. This local differentiation allows each feature type to be optimized independently, resolving the contradiction between achieving small pitch for metal lines and maintaining manufacturability for contacts/vias.
Solution Approach 2:
The patent transitions from requiring uniform pitch across all features to allowing pitch variation in different spatial dimensions and feature types. By permitting metal lines to have smaller pitch than contacts/vias, the system adds dimensional flexibility to the pitch parameter, enabling optimization for each feature type's specific requirements.
2Productivity
If feature sizes and spacing are scaled down to increase density, then more components fit on substrate, but features approach or exceed diffraction limit of photolithographic equipment
Solution Approach 1:
The patent changes the pitch parameter differently for different feature types: metal interconnect lines are allowed smaller pitch while contacts and vias maintain larger pitch. This parameter differentiation enables overall circuit density to increase while keeping individual feature dimensions within manufacturable ranges, thus increasing chips per substrate without exceeding equipment capabilities.
3Manufacturing precision
If minimum pitch for contacts and vias is reduced to match metal line pitch, then orthogonal arrays achieve maximum density, but photolithographic equipment cannot resolve such small pitches
Solution Approach 1:
The patent applies partial density optimization by allowing metal lines to achieve minimum pitch while contacts and vias use a slightly larger, more manufacturable pitch. This partial application of minimum pitch to only metal lines (rather than all features) achieves sufficient density while maintaining lithography feasibility for contacts and vias.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more efficient use of space in integrated circuits, increasing the number of chips per substrate and reducing manufacturing costs by enabling tighter pitch configurations for vias and contacts, thus enhancing the connectivity and density of metal interconnects.
Implementation Method 1
patterns for forming horizontal metal lines, vertical metal vias and vertical metal contacts are generated by photolithographic processes
Implementation Method 2
Feature sizes and spacing smaller than 100 nanometers are often close to a diffraction limit of photolithographic equipment used to generate their patterns
Data Source
AI summary
Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays.