Semi-floating Gate Transistor Fabrication Without Substrate Etching
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Solution Overview
Problem
The existing methods for manufacturing semi-floating gate transistors cause damage to the crystalline structure of the substrate during etching, leading to increased leakage current and power consumption, and limit the miniaturization of the floating gate transistor due to etching-related inaccuracies and alignment issues.
Innovation Solution
A semi-floating gate transistor structure is developed with a P-type doped floating gate disposed on the substrate surface, eliminating the need for substrate etching and incorporating a heavily doped N-type region to form a pn-junction diode, which improves carrier concentration and erase speed while maintaining precise alignment without substrate damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If substrate etching is performed to form a groove for the floating gate electrode, then the floating gate can be formed in the substrate, but the crystalline structure of the substrate is damaged, leading to increased leakage current and power consumption
Solution Approach 1:
The invention extracts the floating gate electrode from the substrate interior and places it on the substrate surface. Specifically, the method forms a groove only in the gate oxide layer (not the substrate), deposits polysilicon to form the floating gate, and then fills the groove with insulating material. This extraction eliminates substrate etching damage while maintaining proper floating gate positioning and electrical isolation through the gate oxide layer.
Solution Approach 2:
The invention segments the groove formation process to affect only the gate oxide layer rather than the substrate. By limiting the etching to the oxide layer and using subsequent insulating material filling, the substrate crystalline structure remains intact, preventing leakage current while still creating the necessary structure for floating gate formation.
2Ease of manufacture
If substrate etching is performed to form the groove, then the floating gate structure can be created, but alignment accuracy is difficult to determine and lithographic mask alignment is adversely affected
Solution Approach 1:
The invention introduces the gate oxide layer as an intermediary layer between the substrate and the floating gate electrode. The groove is formed in this intermediary layer rather than the substrate, providing a clear, well-defined etching target that improves alignment accuracy. The oxide layer serves as a mediator that enables precise groove formation without compromising substrate integrity or alignment determination.
3Productivity
If the floating gate transistor size is reduced to increase integration density, then more devices can be integrated, but etching-related inaccuracies and alignment issues become more significant
Solution Approach 1:
By extracting the floating gate formation from substrate etching and placing it on the surface with groove formation limited to the gate oxide layer, the invention eliminates the limiting factor (substrate etching accuracy) that constrains feature size reduction. This enables continued scaling to smaller dimensions while maintaining manufacturing precision through the intermediary oxide layer approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current and power consumption by avoiding substrate etching and enhances the integration density of semiconductor devices by maintaining the P-type doped floating gate over the substrate surface, ensuring accurate alignment and increased carrier flow rates.
Implementation Method 1
the semi-floating-gate transistor with a silicon body TFET quantum tunneling effect
Data Source
AI summary
A semi-floating gate transistor structure includes a substrate, a first N-well region and a second N-well region separated from each other in the substrate, and a gate oxide layer on the substrate. The gate oxide layer includes a separation groove disposed on the first N-well region. The semi-floating gate transistor structure further includes a P-type doped floating gate having a first portion filling the separation groove and a second portion integrally formed on the first portion. The first portion of the P-type doped floating gate and the first N-well region form a pn-junction diode.