Semipermeable Barrier for Partial Data Computation

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Solution Overview

Problem

In parallel computing systems using the Message Passing Interface (MPI), the impermeable synchronization barrier causes computation to stall until the entire data array is received, even though continuous data regions may be available in the receive buffer.

Innovation Solution

Implementing a semipermeable barrier that allows partial computation on smaller data chunks as soon as they arrive at the receive buffer, delaying actual blocking until the whole array has passed through the barrier.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an impermeable synchronization barrier is used to ensure data completeness, then data reliability is improved, but computation speed deteriorates due to stalling until the entire array is received

Engineering Contradiction:
Improvedata completenessVSAvoidcomputation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent divides the receive buffer into multiple data regions corresponding to different data chunks. Each region can be independently processed when its data arrives, rather than waiting for the entire array. This segmentation allows computation to proceed on available data portions while maintaining the barrier's reliability guarantee for the complete dataset.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs computation on data chunks as soon as they arrive in the receive buffer, before the entire array is received. This preliminary computation action occurs in advance of what would traditionally be required (waiting for complete array arrival), thereby improving computation speed while the barrier ensures eventual data completeness.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If computation waits for the entire data array to be received, then data accuracy is improved, but resource utilization deteriorates due to idle computation resources

Engineering Contradiction:
Improvedata accuracyVSAvoidresource utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The receive buffer is segmented into multiple independent data regions, each associated with specific data chunks. This allows computation resources to be utilized on regions that have received data, while other regions continue to receive data. The segmentation enables partial resource utilization without compromising the accuracy requirement for the complete array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables continuous computation action on data chunks as they arrive, rather than having computation resources idle until the entire array is received. The useful action (computation) continues progressively as data becomes available, improving resource utilization while the barrier operation ensures eventual completion with accurate results.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If a traditional barrier operation is used to synchronize data reception, then synchronization reliability is improved, but processing efficiency deteriorates due to blocking until the whole array is received

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The barrier operation is transformed from an all-or-nothing blocking mechanism into a segmented operation where each data region in the receive buffer can be independently processed. This segmentation allows processing to proceed efficiently on available data while the barrier maintains its synchronization reliability for the complete array reception.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs computation actions on data chunks preliminarily, as soon as they arrive in the receive buffer, rather than waiting for the complete array. This preliminary processing improves efficiency while the barrier operation ensures that synchronization reliability is maintained for the entire array once reception is complete.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12299501B2Technologies for managing data wait barrier operations
Publication Date: 2025.05.13 INTEL CORP
  • US12299501B2 patent drawing
  • US12299501B2 patent drawing
  • US12299501B2 patent drawing

AI summary

Technologies for managing data wait barrier operations include starting a receive operation associated with a receive buffer of a compute node that includes a plurality of chunks of data received from a sender compute node. Each of the plurality of chunks of data may be received in an out-of-order sequence relative to an order in which they were transmitted from the sender compute node. The compute node may determine whether a chunk of data in the receive buffer satisfies a condition to be met prior to performing one or more data wait barrier operations to be performed by the compute node to process the chunk of data and, if so, perform a partial computation over the chunk of data.