Sense Amp Enable Signal Timing Adjustment in Memory Circuits
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Solution Overview
Problem
Existing memory circuits face challenges in reducing power consumption and implementing efficient designs due to unpredictable precharge levels and bitline mismatches, leading to incorrect results and increased silicon area overhead.
Innovation Solution
A segmented memory architecture with a sense amp enable generation module that adjusts the timing of the sense amplifier enable signal based on bitline sense feedback, using test columns to determine optimal delay for accurate data reading and minimizing faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a segmented memory architecture is used, then power consumption is reduced and read speed is improved, but silicon area overhead increases due to requiring separate bitline conditioners and column multiplexers for each segment
Solution Approach 1:
The bitline conditioner circuit is designed to perform multiple functions: it conditioners bitlines for normal memory operations and also serves as a test column selector for fault detection. This multi-functionality eliminates the need for separate dedicated test column selector circuits in each segment, reducing the overall silicon area overhead while maintaining the power consumption benefits of segmented architecture.
2Reliability
If test columns are added for fault detection, then reliability is improved, but device complexity and silicon area increase
Solution Approach 1:
The test column selection functionality is merged with the existing bitline conditioner circuit. The bitline conditioner's select lines are used to choose between regular memory columns and test columns, eliminating the need for separate test column selector circuits. This integration maintains fault detection capability while reducing device complexity and silicon area.
Solution Approach 2:
The bitline conditioner circuit serves itself by using its existing select line infrastructure to also perform test column selection. The same circuit resources that condition bitlines for normal operations are repurposed to select test columns when needed, eliminating the need for additional dedicated test selection circuitry.
3Area of stationary object
If NMOS transistors are used in bitline conditioner and column MUX, then silicon area is reduced, but precharge level becomes unpredictable due to NMOS leakage and voltage variations
Solution Approach 1:
The patent incorporates feedback mechanisms where the bitline conditioner circuit monitors its own operation and adjusts timing signals accordingly. The sense amp enable generation module uses feedback from bitline sense activity to dynamically adjust the timing of enable signals, compensating for NMOS leakage and voltage variations to maintain stable precharge levels while keeping the circuit compact.
Solution Approach 2:
The circuit transitions from static timing signals to dynamic, adaptive timing control. The sense amp enable generation module adjusts the timing of enable signals in real-time based on actual bitline conditions, allowing the circuit to compensate for NMOS transistor variations and maintain reliable operation with reduced silicon area.
Data Source
AI summary
A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that addresses a selected one of the array of memory cells in a selected one of the plurality of columns in response to a memory address. A sense amplifier generates a data output by sensing a differential voltage from the corresponding bitline pair of the selected one of the plurality of columns in response to a sense amp enable signal. A sense amp enable signal generator generates the sense amp enable signal with adjustable timing, based on sense amp feedback signals.