Sense Amplifier with Asymmetric Capacitive Load for Memory Integration
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Solution Overview
Problem
Conventional semiconductor memory devices with open bit line structures require dummy cells at memory block edges and rely on complementary bit lines for sensing, which limits integration density and increases power consumption, especially with the half power supply voltage pre-charge scheme being less studied.
Innovation Solution
A semiconductor memory device design that eliminates the need for complementary bit lines by using a sense amplifier with a first node connected to a bit line and a second node without electrical connection to any bit line, employing isolation transistors, and utilizing either VDD or VSS pre-charge schemes to reduce power consumption and enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an open bit line structure is used to integrate more memory cells in the same area, then memory cell integration density is improved, but dummy cells must be added at edge memory blocks which increases device complexity
Solution Approach 1:
The patent extracts and eliminates the complementary bit line from the sense amplifier structure, using only a single bit line connected to the first node while the second node remains unconnected to any bit line. This removal of the complementary bit line eliminates the need for dummy cells at edge memory blocks, resolving the contradiction between integration density and device complexity
Solution Approach 2:
The patent introduces asymmetry in the sense amplifier by creating unequal capacitive loads between the first node (connected to bit line with larger capacitance) and the second node (unconnected to bit line with smaller capacitance). This asymmetric design enables the sense amplifier to function with a single bit line without requiring dummy cells, thereby improving integration density while avoiding increased device complexity
2Reliability
If complementary bit lines are used for sensing in conventional sense amplifiers, then sensing function is achieved, but power consumption increases due to the need for pre-charging both bit lines
Solution Approach 1:
The patent removes the complementary bit line from the sensing structure, retaining only a single bit line connected to the first node. The second node operates without connection to any bit line, eliminating the need to pre-charge a second bit line and thereby reducing power consumption while maintaining the sensing function through the asymmetric capacitive load design
Solution Approach 2:
The patent changes the pre-charge voltage parameter from conventional 1/2 VDD to either VDD or ground voltage. This parameter change, combined with the asymmetric capacitive load configuration, enables the sense amplifier to achieve reliable sensing with reduced power consumption by pre-charging only the necessary node without requiring a complementary bit line
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for higher memory cell integration density without dummy cells and reduces power consumption by eliminating the need for complementary bit lines and optimizing pre-charge schemes, improving overall efficiency and reducing power usage.
Implementation Method 1
The sense amplifier has a capacitive load less than that of the bit line, and the capacitive load of the bit line is about 10 times greater than that of the second node
Implementation Method 2
the isolation transistor connects the first node to the bit line if the word line is activated
Data Source
AI summary
A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.