Bit Line Sense Amplifier Asymmetric Delay Offset Compensation
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Solution Overview
Problem
Bit line sense amplifiers in memory devices face challenges in accurately sensing and amplifying voltage differences due to offset issues, which are exacerbated by variations in power supply voltage, leading to incorrect operations.
Innovation Solution
The implementation of an integrated circuit with a bit line sense amplifier that generates pull-up and pull-down enable signals with delayed activation times, where the first delay path has a constant delay amount and the second delay path's delay varies inversely with power supply voltage, allowing for optimized voltage difference amplification across bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bit line sense amplifier uses conventional equal delay paths for pull-up and pull-down enable signals, then the circuit structure is simple, but the offset is large and data sensing accuracy deteriorates
Solution Approach 1:
The patent introduces asymmetric delay paths where the first delay path for the pull-up enable signal has a different delay value than the second delay path for the pull-down enable signal. Specifically, the first delay value is set to be smaller than the second delay value, creating an intentional asymmetry that compensates for the offset effect and improves data sensing accuracy without requiring complex additional circuitry.
Solution Approach 2:
The patent adjusts the delay parameters of the enable signal paths to optimize performance. By setting specific delay values for the first and second delay paths (where the first delay value < second delay value), the circuit compensates for voltage threshold variations and reduces offset, thereby improving sensing accuracy through parameter optimization rather than structural complexity.
2Reliability
If the bit line sense amplifier operates with fixed delay paths, then the circuit is simple to implement, but performance deteriorates under power supply voltage variation
Solution Approach 1:
The patent implements dynamic delay control where the delay values of the first and second delay paths are designed to vary in response to power supply voltage changes. The first delay path is configured with a first delay value that is smaller than the second delay value, and this delay difference is optimized to compensate for voltage variations, ensuring reliable operation across different power conditions without requiring complex adaptive circuits.
3Measurement precision
If the pull-up and pull-down enable signals are activated simultaneously, then the control logic is simple, but voltage difference amplification is inaccurate due to offset
Solution Approach 1:
The patent applies preliminary action by introducing different delay values for the pull-up and pull-down enable signals before they are generated. The first delay path for the pull-up enable signal is configured with a smaller delay than the second delay path for the pull-down enable signal, creating an intentional timing difference that compensates for offset effects and enables accurate voltage difference amplification while maintaining simple control logic.
Data Source
AI summary
An integrated circuit may include an amplifier circuit configured to receive a pull-up voltage in response to a pull-up enable signal, receive a pull-down voltage in response to a pull-down enable signal, and amplify a voltage difference between a first line and a second line through the pull-up and pull-down voltages; a first delay path configured to generate the pull-up enable signal by delaying an input signal; and a second delay path configured to generate the pull-down enable signal by delaying the input signal, wherein a change in a delay of the first delay path due to variation of a power supply voltage is smaller than a change in a delay of the second delay path due to the variation.