Current Sense Amplifier Biasing for Solid State Memory Power
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Solution Overview
Problem
There is a need for memory devices with high data transfer rates and low power consumption, particularly in portable electronic devices, where the sense amplifier's power usage affects both data transfer speed and power efficiency.
Innovation Solution
The use of current sense amplifiers with varying bias currents, where some amplifiers are provided with more power to detect the first bit faster and others with less power to detect subsequent bits, allowing for efficient data transfer without significantly impacting overall data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sense amplifiers use uniform high bias current to detect all bits, then data transfer rate is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by assigning different bias current levels to different sense amplifiers based on their position in the data bit sequence. Specifically, sense amplifiers detecting earlier bits (e.g., first bit) receive higher bias currents for faster detection, while those detecting later bits receive lower bias currents. This localized differentiation resolves the contradiction by optimizing speed where it matters most (first bit detection) while reducing power consumption in less critical positions.
Solution Approach 2:
The patent segments the sense amplifier array into multiple groups or categories based on their detection priority. Instead of treating all sense amplifiers uniformly, the system divides them into segments with different power allocation levels. This segmentation allows the system to apply different power strategies to different portions of the data detection process, achieving a balance between overall speed and power consumption.
2Use of energy by moving object
If sense amplifiers use varying bias currents to prioritize first bit detection, then power consumption is reduced, but data transfer rate may be impacted
Solution Approach 1:
The patent changes the parameter of bias current dynamically based on the detection sequence and position. By adjusting the bias current parameter according to which bit is being detected and its position in the sequence, the system optimizes the trade-off between power consumption and detection speed. The first bit detection uses higher current parameters for speed, while subsequent bits use lower current parameters for power savings, with the overall data transfer rate maintained through careful parameter selection.
Data Source
AI summary
Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.