Sense Amplifier Bit Line Precharging for DRAM Access
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Solution Overview
Problem
Conventional 3-transistor single-ended sense amplifiers for DRAM cells face issues due to threshold voltage variations in NMOS transistors, leading to complex routing of read and write bit lines and a large area requirement, which affects data sensing accuracy and efficiency.
Innovation Solution
A sense amplifier that precharges the bit line to a voltage equal to or higher than the threshold voltage of the sensing transistor, using a simplified configuration without PMOS transistors and reducing the complexity of bit line routing, allowing for efficient data sensing by selectively connecting bit lines to global bit lines through signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3-transistor single-ended sense amplifiers are used, then data sensing can be achieved, but threshold voltage variations in NMOS transistors cause complex routing of read and write bit lines and increase area requirement
Solution Approach 1:
The patent extracts and eliminates the PMOS transistor from the conventional 3-transistor sense amplifier configuration, leaving only NMOS transistors. This simplification removes the source of threshold voltage variation issues between different transistor types, allowing for simpler bit line routing while maintaining sensing functionality through the remaining NMOS transistors
Solution Approach 2:
The patent segments the bit line routing into distinct read bit lines and write bit lines with separate access paths, allowing independent optimization of each path. This segmentation enables simpler routing for each line type while maintaining the ability to sense data accurately through the segmented architecture
2Reliability
If conventional 3-transistor single-ended sense amplifiers are used, then data sensing can be achieved, but the area requirement increases
Solution Approach 1:
By removing the PMOS transistor from the conventional 3-transistor configuration, the patent reduces the transistor count to 2 NMOS transistors. This extraction of the unnecessary PMOS component directly reduces the occupied area while preserving the essential data sensing capability through the simplified NMOS-only architecture
Solution Approach 2:
The patent merges the read and write bit line access functions into a unified sense amplifier structure using only NMOS transistors. This merging of functions into a single simplified architecture reduces the overall area requirement compared to separate dedicated read and write paths with PMOS transistors
3Reliability
If conventional 3-transistor single-ended sense amplifiers are used, then data sensing can be achieved, but the routing complexity affects access efficiency
Solution Approach 1:
The patent extracts and removes the PMOS transistor that caused threshold voltage variations and routing complexity. This extraction enables more direct and efficient bit line routing paths, improving data access speed and efficiency while maintaining reliable sensing functionality through the simplified NMOS transistor architecture
Data Source
AI summary
A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line.