Sense Amplifier Bit-Line Boosting Without Charge Pumps
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Solution Overview
Problem
Existing technologies fail to efficiently address the need for phase-change memory devices with improved performance and reliability, particularly in the context of semiconductor devices and semiconductor devices, by optimizing the integration of phase-change memory cells and enhancing the sensing mechanism for reliable data storage and retrieval.
Innovation Solution
The integration of a novel sense amplifier circuit that includes a first and second input terminal, a sensing circuit, and a control circuitry to dynamically adjust the bit line pre-charge voltage based on system supply voltage levels, utilizing boosting capacitors and a voltage detector to optimize power consumption and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If charge pumps are used to boost bit line voltage, then voltage boosting capability is improved, but power consumption and area requirements increase
Solution Approach 1:
The patent extracts the voltage boosting function from the traditional charge pump circuit and relocates it to the sense amplifier circuit. By removing the separate charge pump component and integrating its functionality into the sense amplifier, the design eliminates the associated power consumption and area overhead while maintaining the necessary voltage boosting capability for bit line precharging.
Solution Approach 2:
The patent merges the voltage boosting function with the sense amplifier circuit by adding boosting capacitors and control logic to the existing sense amplifier structure. This integration allows the sense amplifier to simultaneously perform its sensing function and provide voltage boosting, eliminating the need for separate charge pump circuits and reducing overall system complexity.
2Reliability
If conventional sense amplifier circuits are used, then sensing capability is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the sense amplifier circuit by introducing a voltage detector that monitors supply voltage levels and dynamically activates or deactivates the boosting capacitors based on operating conditions. This dynamic adaptation allows the circuit to maintain sensing capability while minimizing power consumption by only activating voltage boosting when necessary, such as when supply voltage drops below threshold levels.
3Area of stationary object
If voltage boosting is implemented without charge pumps, then area requirements are reduced, but voltage regulation capability may be compromised
Solution Approach 1:
The patent incorporates a voltage detector that continuously monitors the supply voltage and provides feedback control for the boosting capacitor activation. When the supply voltage drops below a predetermined threshold, the voltage detector activates the boosting capacitors to compensate for the voltage drop, ensuring stable bit line precharging voltage. This feedback mechanism maintains voltage regulation capability while avoiding the use of area-intensive charge pump circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves reduced power consumption and area requirements while effectively boosting bit line voltage, enhancing the reliability and speed of phase-change memory operations without relying on charge pumps, thereby improving overall memory device performance.
Implementation Method 1
A first boosting capacitor has a first terminal coupled to the first input terminal and a second terminal coupled to a floating node. A second boosting capacitor has a first terminal coupled to the second input terminal and a second terminal coupled to the floating node.
Data Source
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AI summary
A sense amplifier circuit (52) for a memory device (10) includes a first input terminal (304L) and a second input terminal (304R) configured for coupling (SWYMPS,L, SWYMPS,R) to a first memory sensing node (302L) and a second memory sensing node (302R), respectively. A sensing circuit (30') is coupled to the first (304L) and second (304R) input terminals and is configured to sense a differential signal therebetween. A first boosting capacitor (CBSTL) has a first terminal coupled to the first input terminal (304L) and a second terminal coupled to a floating node (62). A second boosting capacitor (CBSTR) has a first terminal coupled to the second input terminal (304R) and a second terminal coupled to the floating node (62). A control circuitry (64, SL, SR) is configured to receive a bit line boosting activation signal (YMPS_PRECH_BST). In response to the bit line boosting activation signal (YMPS_PRECH_BST) having a first value, the first terminals of the first (CBSTL) and second (CBSTR) boosting capacitors are coupled to a regulated supply node (108) that provides a regulated supply voltage (VREG) and the floating node (62) is driven to a ground voltage. In response to the bit line boosting activation signal (YMPS_PRECH_BST) having a second value, the first terminals of the first (CBSTL) and second (CBSTR) boosting capacitors are decoupled from the regulated supply node (108) and the floating node (62) is driven to the regulated supply voltage (VREG).