DRAM Sense Amplifier Bitline Isolation for Power Reduction
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Solution Overview
Problem
Current DRAM devices require frequent data refreshing, which consumes significant power, particularly in battery-operated devices like mobile phones and laptops, necessitating the development of power-efficient methods for refreshing data stored in DRAM devices.
Innovation Solution
The implementation of a semiconductor memory device with a sense amplifier and bitline isolation mechanism that controls the electrical connection and disconnection of bitlines during the refresh operation, allowing for efficient power management by disconnecting one bitline while the other remains connected, thereby reducing power consumption during the signal amplification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both bitlines are allowed to fully develop during refresh operation, then data integrity is maintained, but power consumption increases significantly
Solution Approach 1:
The patent divides the bitline pair into two separate controllable paths using isolators. Instead of treating both bitlines uniformly, the isolator selectively connects or disconnects each bitline from its corresponding sense amplifier input based on the refresh operation state. This segmentation allows one bitline to be isolated while the other remains connected, reducing power consumption while maintaining data integrity through differential sensing.
Solution Approach 2:
The isolator implements different connection states for different parts of the circuit during refresh operations. Specifically, the first bitline can be connected to the first sense amplifier input while the second bitline is disconnected from the second input, or vice versa. This local differentiation in connection quality allows the circuit to maintain necessary signal paths while isolating unnecessary ones, thereby reducing overall power consumption without compromising data integrity.
2Reliability
If frequent refresh operations are performed to retain stored data, then data retention is ensured, but power consumption increases
Solution Approach 1:
The patent implements periodic refresh operations with optimized timing control through the isolator mechanism. The isolator enables selective connection/disconnection of bitlines during each refresh cycle, allowing the system to perform necessary refresh operations at periodic intervals while minimizing power consumption during each cycle. This periodic action with optimized duty cycle maintains data retention while reducing overall power usage compared to continuous full-bitline operation.
3Use of energy by moving object
If the isolator disconnects both bitlines during refresh, then power consumption is minimized, but sensing capability is lost
Solution Approach 1:
The patent extracts or removes only the unnecessary connection path during refresh operations while maintaining the necessary one. The isolator selectively disconnects one bitline from its sense amplifier input while keeping the other bitline connected. This extraction approach removes the harmful power consumption element without removing the useful sensing capability, allowing the system to operate efficiently while maintaining full sensing functionality when needed.
Data Source
AI summary
A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.