Sense Amplifier Buffer for Transistor Mismatch Minimization
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Solution Overview
Problem
Semiconductor memory devices experience invalid sensing due to mismatch in threshold voltage between transistors in cross-coupled latch type sense amplifiers, leading to operational failures.
Innovation Solution
Incorporating an equalization transistor as a buffer between PMOS and NMOS transistors in the sense amplifier, with specific spacing to minimize the impact of impurity implantation mismatch, and optionally using a dummy transistor to further prevent mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are formed in pairs with different distances from the photoresist sidewall, then manufacturing process is simplified, but transistor mismatch occurs due to different impurity implantation
Solution Approach 1:
The patent intentionally introduces asymmetry by adding a buffer region only to one side of the transistor pair (the side closer to the photoresist sidewall). This asymmetric modification compensates for the asymmetric impurity implantation effect, ensuring that both transistors in the pair receive equivalent net impurity doses despite their different initial positions relative to the sidewall.
Solution Approach 2:
The buffer region is applied locally only to specific transistors that require compensation. Rather than modifying the entire layout uniformly, the patent selectively adds buffer regions to transistors on one side of the pair while leaving transistors on the other side unchanged, thereby achieving precise local compensation for impurity implantation variations.
2Area of stationary object
If transistors are placed closer to the photoresist sidewall, then device area is reduced, but impurity implantation mismatch increases
Solution Approach 1:
The patent modifies the physical parameter of transistor spacing by introducing a buffer region that increases the distance between certain transistors and the photoresist sidewall. This parameter change (increasing spacing asymmetrically) compensates for the harmful effects of proximity to the sidewall during impurity implantation, thereby maintaining manufacturing precision while allowing compact overall layout.
3Manufacturing precision
If symmetric layout is used for transistor pairs, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the transistor layout into two distinct groups: transistors that require buffer regions and transistors that do not. This segmentation allows the design to achieve effective symmetry in terms of impurity implantation compensation without requiring complete geometric symmetry in the layout, thereby reducing overall device complexity while maintaining manufacturing precision.
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized.