Sense Amplifier Bus Sharing Without Multiplexer Readout Delay
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Solution Overview
Problem
Multiplexing in large memory arrays introduces delays, synchronization issues, and increases semiconductor area occupation, leading to spurious switching and increased consumption.
Innovation Solution
Implement a method where a single data bus is retained by the last sense amplifier, which avoids multiplexers by one sense amplifier, which avoids multiplexers by one sense amplifier, which avoids multiplexers by sharing data outputs from multiple memory banks over a common data bus and using a sense amplifier to autonomously control the bus without multiplexers, maintaining a high-impedance state during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiplexing is used to share data buses from multiple memory banks, then the number of data buses is reduced and semiconductor area is saved, but access time increases due to additional multiplexing delay
Solution Approach 1:
The patent extracts the multiplexing function from a separate multiplexer component and integrates it directly into the sense amplifier circuitry. Each sense amplifier includes an output driver stage with switches that directly connect to the common data bus, eliminating the need for a separate multiplexer and its associated propagation delay while still achieving bus sharing functionality.
Solution Approach 2:
The patent merges the data output function with the bus control function by integrating the output driver stage directly into each sense amplifier. The sense amplifiers directly drive the common data bus through switches controlled by bus control signals, combining what were previously separate functions (data output from memory banks and multiplexing control) into a unified circuit architecture.
2Area of stationary object
If multiplexing is used to share data buses from multiple memory banks, then the number of data buses is reduced, but synchronization issues arise and spurious switching occurs
Solution Approach 1:
The patent implements feedback control through bus control signals that are generated based on the read operation status. When a read operation is completed, the corresponding sense amplifier generates a signal that controls the switch to disconnect from the bus. This feedback mechanism ensures that only the active sense amplifier connects to the bus, preventing spurious switching and ensuring reliable data transfer without requiring complex external multiplexing control logic.
3Area of stationary object
If multiplexers are used to share data buses, then data bus sharing is achieved, but device complexity increases due to additional logical gates and routing
Solution Approach 1:
The patent removes the separate multiplexer component and its associated control logic from the system. Instead, each sense amplifier directly controls its connection to the common data bus through integrated switches, eliminating the need for external multiplexer control signals and reducing the overall circuit complexity while maintaining bus sharing capability.
Solution Approach 2:
The sense amplifiers are designed to perform multiple functions: data output, bus control, and switch management. Each sense amplifier can independently control its connection to the common data bus through its integrated output driver stage, making the sense amplifiers universal components that handle both data transmission and bus arbitration without requiring separate multiplexer logic.
Data Source
AI summary
A data readout method, corresponding circuit, and memory device are provided. In an example, plural memory banks in a memory device share a common data readout bus via respective sense amplifiers. Data are read from the memory banks in a sequence of readout operations wherein, during each readout operation, the sense amplifier of one of the memory banks takes control over the common data readout bus and data are read from that one memory bank via the sense amplifier taking control over the common data readout bus, while the sense amplifiers of the other memory banks are set to a high impedance state.