Sense Amplifier Cache Memory for Semiconductor Devices
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Solution Overview
Problem
Semiconductor memory devices face limitations in using sense amplifiers as cache memory due to data destruction during refresh operations, and providing separate cache memory for each unit block is costly and complex.
Innovation Solution
A semiconductor memory device configuration with switch means and control means to redirect data between sense amplifiers, allowing data to be saved and written back without destroying it during refresh operations, using shared and unshared sense amplifiers and cache memories to facilitate efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sense amplifiers are used as cache memory, then data storage capability is improved, but data is destroyed during refresh operations
Solution Approach 1:
The sense amplifier rows are divided into two functional groups: cache memory rows (attached to unit blocks) and saving destination rows (not attached to unit blocks). This segmentation allows data to be stored in cache rows while preserving copies in saving rows during refresh operations, resolving the conflict between using sense amplifiers as cache and maintaining data integrity during refresh.
2Reliability
If separate cache memory is provided for each unit block, then data protection during refresh is improved, but cost and chip area increase
Solution Approach 1:
The saving destination sense amplifier rows serve multiple functions: they act as backup storage during cache operations, provide refresh targets for protected data, and can be shared across multiple unit blocks. This multi-functionality eliminates the need for dedicated cache memory per unit block, reducing chip area while maintaining data protection.
3Area of stationary object
If common cache memory is used for large number of unit blocks, then chip area is reduced, but control and configuration complexity increases
Solution Approach 1:
The system dynamically reconfigures the connection state of sense amplifier rows to unit blocks using switch means. Rows can be attached or detached from unit blocks based on operational mode (cache mode vs. saving mode), allowing a common set of sense amplifiers to serve multiple unit blocks without permanent complex interconnections, thus reducing both area and control complexity.
Data Source
AI summary
A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory.